A duty cycle measuring circuit, the circuit comprising a synchronizer and a measurer, the synchronizer arranged such that when a signal to be measured comprising pulses having a pulse width and a pulse period is input to the synchronizer, synchronizing signals corresponding to each of pulse rising edge, pulse falling edge, pulse period start and pulse period end are output from the synchronizer, each synchronizing signal comprising a rising or falling edge, wherein the synchronizing signal outputs from the synchronizer are input to the measurer, and wherein the measurer is arranged to provide two measurement outputs based on the synchronizing signal inputs from the synchronizer, the measurement outputs comprising a first measurement output signal indicative of a pulse period measurement of the signal to be measured and a second measurement output signal indicative of a pulse width measurement of the signal to be measured.

A signal processing device is described, with a signal input for receiving an input signal, a first trigger unit generating a trigger signal based upon a first trigger event in the input signal and an acquisition memory for acquiring the input signal at least based upon the trigger signal so as to provide an acquired signal. The signal processing device also comprises a second trigger unit connected to the acquisition memory. The second trigger unit is adapted to process the acquired signal according to a second trigger. The second trigger unit is adapted as a zone trigger unit applying a zone trigger. Further, a method of applying a zone trigger is described.

A signal processing device is described, with a signal input for receiving an input signal, a first trigger unit generating a trigger signal based upon a first trigger event in the input signal and an acquisition memory for acquiring the input signal at least based upon the trigger signal so as to provide an acquired signal. The signal processing device also comprises a second trigger unit connected to the acquisition memory. The second trigger unit is adapted to process the acquired signal according to a second trigger. The second trigger unit is adapted as a zone trigger unit applying a zone trigger. Further, a method of applying a zone trigger is described.

A testing circuit includes: a first sampling module configured to receive a to-be-tested pulse signal, and generate a first sampled signal according to the pulse signal; and a second sampling module configured to receive the pulse signal, and generate a second sampled signal according to the pulse signal. The second sampled signal and the first sampled signal have a phase difference, the phase difference being equal to a pulse width of the pulse signal.

A clock phase correction circuit includes: a first variable delay circuit suitable for delaying a second source clock to generate a third clock; a first pulse generation circuit suitable for generating a first pulse signal that is activated from an edge of a first clock to an edge of the third clock and generating a second pulse signal that is activated from the edge of the third clock to the edge of the first clock; and a first delay value adjustment circuit suitable for detecting whether a ratio of a pulse width of the first pulse signal to a pulse width of the second pulse signal is greater or less than 1:3 to produce a detection result and adjusting a delay value of the first variable delay circuit based on the detection result.

A semiconductor device according to the present invention has a PLL circuit which includes: a phase comparison part that detects the phase difference between a reference signal and an oscillation signal to produce a phase difference signal indicative of the phase difference in binary and then output the produces signal to outside through a first external terminal; a voltage conversion part that applies, to a phase difference voltage node, a phase difference voltage having a voltage value corresponding to the phase difference represented by the phase difference signal; an oscillation part that produces, as an oscillation signal, a signal having a frequency depending on the phase difference voltage; and a correction circuit that supplies a correction current to the phase difference voltage node, and upon reception of a test control signal at a second external terminal, supplies a current depending on the test control signal to the phase difference voltage node as a correction current.

Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.

An identification method is an identification method for use in an identification apparatus that identifies types of brushless DC motors each including a circuit board on which a terminal for tachometer is mounted. The duty ratios of pulses outputted from the terminals for tachometer vary among multiple types of brushless DC motors. The identification method includes: supplying a power supply voltage from the identification apparatus to a brushless DC motor; inputting pulses outputted from the terminal for tachometer of the circuit board to the identification apparatus; obtaining the duty ratio of the pulses as a unique information piece of the brushless DC motor; and identifying the type of the brushless DC motor based on the unique information piece of the brushless DC motor.

A method is provided for testing switch signals of an inverter of an electric machine of a drive system of a motor vehicle. The electric machine is controlled via a pulse-width modulation generated by a control unit using a target duty cycle and a triangular-waveform voltage sequence. An actual duty cycle of a current pulse-width modulation is continuously ascertained from the switch signals and compared with the target duty cycle of the control unit.

A feature detection system, the system comprising: at least one processor in operative communication with a signal source, said processor further comprising at least one non-transitory storage medium, wherein at least one non-transitory storage medium contains instructions configured to cause the processor to: apply a joint group sparse denoising and delay estimation approach to a signal received from said signal source; and output statistics regarding the signal, wherein the joint group sparse denoising and delay estimation approach comprises; using the following equation: $\left\{x^{*},{?}^{*}\right\}=\underset{x,?}{\mathrm{argmin}}\left\{\frac{1}{2}\underset{j=1}{\overset{M}{.Math.}}{.Math.y_j-x.Math.}_2^2+\underset{i=0}{\overset{N}{.Math.}}{?}_i{?}_i\left(D_i^{l_i}x\right)\right\}$
where: ?.sub.i are regularization functions; ?y?x?.sub.2.sup.2 is a data-fidelity term and, in embodiments, is chosen as the least-square term; l.sub.i are real numbers; D.sub.i are operators, which may be linear filters that can be written in matrix form; ?.sub.i are regularization parameters; and x*,?* represent estimates of at least one tr