In order to generate a false failure in a logic circuit without adding a new circuit to the logic circuit, a semiconductor device includes a plurality of test points includes a test point flip-flop to fix a target node within the logic circuit to a predetermined logic level when the flip-flop holds a predetermined value. A scan chain is configured by sequentially coupling a plurality of test point slip-flops. A failure injection circuit injects a failure into the target node during the normal operation of the logic circuit, by generating failure data and by setting the generated failure data to the scan chain through a scan-in node of the scan chain.

Embodiments of the present disclosure describe semiconductor equipment devices having a metal workpiece and a diamond-like carbon (DLC) coating disposed on a surface of the metal workpiece, thermal semiconductor test pedestals having a metal plate and a DLC coating disposed on a surface of the metal plate, techniques for fabricating thermal semiconductor test pedestals with DLC coatings, and associated configurations. A thermal semiconductor test pedestal may include a metal plate and a DLC coating disposed on a surface of the metal plate. The metal plate may include a metal block formed of a first metal and a metal coating layer formed of a second metal between the metal block and the DLC coating. An adhesion strength promoter layer may be disposed between the metal coating layer and the DLC coating. Other embodiments may be described and/or claimed.

Provided is a method for testing a semiconductor device having an A/D converter, the method includes supplying a sinusoidal analog test signal S1 to an A/D converter, storing a group S2 of output codes generated by the A/D converter over a period with an integer K multiple duration of the cycle of the sine wave, in response to the analog test signal S1, and generating a histogram of the stored group S2 of the output codes, and evaluating the A/D converter on the basis of the histogram.

A substrate rotator configured to rotate one or more substrates includes a body, a body actuator coupled to the body and configured to rotate the body, and a first and second gripper coupled to the body. A substrate edge metrology system that measures side chips or other defects on all sides of the substrate is also described. The metrology system includes two metrology stations and the substrate rotator. Methods for measuring side chips or other defects on a substrate are also provided. The method includes performing metrology on a first set of sides of the first substrate, rotating the first substrate by a first angle, and performing metrology on the second set of sides of the first substrate.

This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of the semiconductor devices.

A method of testing an integrated circuit of a device is described. Air is allowed through a fluid line to modify a size of a volume defined between the first and second components of an actuator to move a contactor support structure relative to the apparatus and urge terminals on the contactor support structure against contacts on the device. Air is automatically released from the fluid line through a pressure relief valve when a pressure of the air in the fluid line reaches a predetermined value. The holder is moved relative to the apparatus frame to disengage the terminals from the contacts while maintaining the first and second components of the actuator in a substantially stationary relationship with one another. A connecting arrangement is provided including first and second connecting pieces with complementary interengaging formations that restricts movement of the contactor substrate relative to the distribution board substrate in a tangential direction.

A method for measuring a current-voltage characteristic (Id-Vds characteristic) representing the relationship between the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage) of a transistor M1 includes setting the drain current Id (or collector current) and the drain-source voltage Vds (or collector-emitter voltage), measuring the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig of the transistor M1 in a switching transient state, and acquiring the current-voltage characteristic (Id-Vds characteristic) of the transistor M1 based on the measurement results of the gate-source voltage Vgs (or gate-emitter voltage) and the gate current Ig.

A test apparatus tests a wafer under test on which devices under test each including magnetoresistive memory or a magnetic sensor are formed. In a test process, the wafer under test is mounted on a stage. In the test process, a magnetic field application apparatus applies a magnetic field B.sub.EX to the wafer under test. A test probe card is used in the test process. Multiple magnetization detection units are formed on a diagnostic wafer. In a diagnostic process of the test apparatus, the diagnostic wafer is mounted on the stage instead of the wafer under test. Each magnetization detection unit is capable of measuring a magnetic field B.sub.EX generated by the magnetic field application apparatus. In the diagnostic process, the diagnostic probe card is used instead of the test probe card.

According to the present invention there is provided an assembly for testing optical devices, the assembly comprising, a light integrating sphere (5a); a mask member (160) defining an inlet window (51) for the light integrating sphere (5a); and a plurality of inlet adaptor members (170), each of which can be selectively arranged to cooperate with the mask member (160) so as to modify the amount of the inlet window (51) through which light can pass into the light integrating sphere (5a), and wherein each the plurality of inlet adaptor members (170) comprise openings (171) having different shapes and/or dimensions. There is further provided a corresponding method for testing parameters of a group of optical devices using the assembly.

An abnormality measuring method and an abnormality measuring apparatus of equipment are provided. The abnormality measuring method includes the following steps: acquiring a feature sequence corresponding to a life cycle according to recipe information and sensing information, wherein the feature sequence includes a plurality of feature subset sequences, and the life cycle is relative to a plurality of process runs; performing repeatedly a life segment analyzing process to acquire a plurality of life segments of the life cycle and each of the plurality of the feature subset sequences corresponding to one of the plurality of life segments; building a corresponding trending distribution of each of the plurality of life segments according to a corresponding feature subset sequence of the life segment; and determining whether to send an alarm message according to a plurality of trending distributions.