A flexible probe card according to the present invention includes a compression layer; a transport layer coupled to the compression layer; and a contact layer coupled to the transport layer. The compression layer is formed of encapsulated closed cell polyurethane foam. The transport layer includes connectors for coupling the flexible probe card to a tester. The contact interface layer includes embedded conductive wires placed in a fixed grid pattern in a silicon rubber layer without a specific connector pattern associated either with the transport layer or a device under test.

A method of testing a semiconductor device having a DC line configured to carry either a DC signal or a DC voltage and a circuit electrically connected to the DC line includes: during a first part of a test sequence, enabling a switch device so as to electrically connect a capacitor to the DC line via the switch device and applying a test signal to the circuit while the capacitor is electrically connected to the DC line; and during a second part of the test sequence, disabling the switch device so as to electrically disconnect the capacitor from the DC line via the switch device, injecting an AC signal onto the DC line after the capacitor is electrically disconnected from the DC line, and measuring a response of the circuit to the AC signal.

A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under test. An upper insulating layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper conductive layer, and a lower surface. A middle conductive layer has an upper surface at least in partial face-to-face contact with the lower surface of the upper insulating layer, and a lower surface.

Provided is an ultrasonic inspection device for inspecting a packaged semiconductor device, The ultrasonic inspection device including an ultrasonic transducer that is disposed to face the semiconductor device; a medium holding unit that is provided at an end of the ultrasonic transducer facing the semiconductor device and holds a medium through which ultrasonic waves are propagated; a stage that moves the position of the semiconductor device relative to the ultrasonic transducer; and an analysis unit that analyzes the reaction of the semiconductor device in accordance with input of the ultrasonic waves from the ultrasonic transducer.

Disclosed is a device for testing components under elevated pressure in which a pressure chamber is provided. The lateral boundary of the pressure chamber included a ring and an annular part, which may move perpendicularly to the plane of the component to be tested. A velvet-like lining is provided on the end face of the annular part or of the ring that faces the component to be tested. The fibers of the lining protrude from the annular part or from the ring toward the component to be tested and bridge the gap between the device and the component.

An object of the present invention is to provide a prober that is able to carry out accurate inspection of semiconductor device in wafer state by reducing the effect of the external noises and the leakage of current and further by eliminating the stray capacitance of the chuck stage against the prober housing. The present invention attains this object by providing a prober comprising a chuck cover conductor that comprises a bottom conductor and a side conductor and an open top, wherein a chuck stage can be contained within a space surrounded by the bottom conductor and the side conductor; an upper cover conductor which has opening through which the conducting support members of the probe for front-side electrodes and the probe for back-side electrodes can be passed, and which is large enough to cover, in a plane view, at least the open top of the chuck cover conductor when the contact member of the probe for front-side electrodes moves relatively within a wafer under inspection; and, a conducting means that brings the chuck cover conductor and the upper cover conductor into contact and makes them electrically continuous.

The disclosure discloses a resistance test method using a Kelvin structure, which includes the following steps: step 1: providing a Kelvin test structure including a tested resistor, a first parasitic resistor, and a second parasitic resistor connected in series; step 2: applying first current to the two current test terminals and simultaneously testing first voltage in the two voltage test terminals; step 3: applying second current in a direction opposite to the direction of the first current to the two current test terminals and simultaneously testing second voltage in the two voltage test terminals; step 4: dividing a difference value obtained by subtracting the second voltage from the first voltage by a difference value between the first current and the second current to obtain the final test value of the tested resistor. The disclosure can reduce the resistance test error.

A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.

To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is provided, the assessment method including:

acquiring a first characteristic correlated with the feedback capacitance and a second characteristic correlated with the feedback capacitance; and

assessing the feedback capacitance based on the first characteristic and the second characteristic. The first characteristic may be a characteristic that corresponds to a withstanding voltage of the semiconductor element, and the second characteristic may be an on-resistance of the semiconductor element. In the assessing, the feedback capacitance may be assessed based on a ratio between the first characteristic and the second characteristic.

A test method for an alignment error includes: providing a substrate, wherein a first conductive layer and a second conductive layer are arranged on the substrate at intervals, and the first conductive layer and the second conductive layer are arranged in a first direction; acquiring a first distance; acquiring a first resistance of the first conductive layer and a second resistance of the second conductive layer; acquiring an actual distance between the first conductive layer and the second conductive layer according to the first distance, the first resistance, and the second resistance; and acquiring a value of the alignment error between the first conductive layer and the second conductive layer based on the actual distance and a standard distance between the first conductive layer and the second conductive layer.