The present invention concerns a method and device for monitoring the gate signal of a power semiconductor (SI), the gate signal of the power semiconductor (SI) being provided by a gate driver (12), generates an expected signal (VGexp) that corresponds to the signal outputted by the gate driver (12) when no deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists, compares the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12), determines if a deterioration of the gate driver (12) and/or of the power semiconductor (SI) and/or of a load linked to the power semiconductor (SI) exists using the result of the comparing of the expected signal (VGexp) and the signal (VGmeas) outputted by the gate driver (12).

An operating condition monitor (100) for monitoring an operating condition of a transistor-based power converter (102), comprising: a sensing apparatus (106) configured to measure a turn-off transient energy of the power converter (102), a processor (108) in communication with the sensing apparatus (106) to receive the measurement of the turn-off transient energy, the processor being configured to: compare the measurement of the turn-off transient energy to a threshold; and issue an event signal based on the comparison to the threshold meeting a comparison criterion. A method (200, 200′) of monitoring an operating state of a transistor-based power converter is also disclosed.

The present disclosure provides a system and a method for monitoring semiconductor manufacturing equipment. The system includes a sensor, a circuit, and an analysis unit. The sensor provides a sensor signal. The circuit receives the sensor signal and generates an input signal. The analysis unit includes a signal management platform, receiving the input signal and performing a first data process to generate a first data signal; a diagnosis subsystem, receiving the first data signal from the signal management platform and performing a health status monitoring process to generate a second data signal; and a decision subsystem, performing a determination process to generate a third data signal according to the second data signal from the diagnosis subsystem. The diagnosis subsystem generates a feedback signal according to the third data signal, and the signal management platform transmits the feedback signal to the semiconductor manufacturing equipment.

A method for predicting failure parameters of semiconductor devices can include receiving a set of data that includes (i) characteristics of a sample semiconductor device, and (ii) parameters characterizing a stress condition. The method further includes extracting a plurality of feature values from the set of data and inputting the plurality of feature values into a trained model executing on the one or more processors, wherein the trained model is configured according to an artificial intelligence (AI) algorithm based on a previous plurality of feature values, and wherein the trained model is operable to output a failure prediction based on the plurality of feature values. Further, the method includes generating, via the trained model, a predicted failure parameter of the sample semiconductor device due to the stress condition.

A chamber module and a test handler including the same are disclosed. The chamber module includes a soak chamber providing a temperature adjusting space for adjusting a temperature of semiconductor devices, an elevating member disposed in the soak chamber and for elevating a tray in which the semiconductor devices are accommodated, a guide member extending in a vertical direction in the soak chamber and for guiding movement of the elevating member, and a temperature adjusting part for adjusting a temperature of the guide member.

A system, method and apparatus for measuring carrier lifetime of a device comprises subjecting a test device to a voltage via a voltage source associated with the test system, disconnecting the test device from the voltage source, measuring the voltage as a function of time, measuring the current as a function of time, and determining a carrier lifetime of the test piece according to the slope of the measured voltage and the measured current.

A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.

A semiconductor device test system may include a body providing an internal space, in which a test device is loaded, and a cover coupled to the body to cover the internal space. The cover may include a first cover including first openings two-dimensionally arranged and a second cover including second openings two-dimensionally arranged. An arrangement of the first openings may be different from an arrangement of the second openings.

An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.

A test circuit includes one or more sensors adapted to be formed on a wafer, each sensor detecting one or more reliability measurement data in a stressed condition; a stress generator controlling the one or more sensors to place the one or more sensors under stress during wafer manufacturing; memory coupled to the one or more sensors to store reliability characteristics under the stressed condition; and an interface coupled to the memory to communicate the wafer characterization data to a tester.