Disclosed is a device for testing components under elevated pressure in which a pressure chamber is provided. The lateral boundary of the pressure chamber included a ring and an annular part, which may move perpendicularly to the plane of the component to be tested. A velvet-like lining is provided on the end face of the annular part or of the ring that faces the component to be tested. The fibers of the lining protrude from the annular part or from the ring toward the component to be tested and bridge the gap between the device and the component.

A testing method and testing system for a semiconductor element are provided. The method includes following steps. A level of a testing electrostatic discharge (ESD) voltage is determined. A plurality of sample components is provided. The testing ESD voltage is imposed on the sample components for testing ESD decay rates of the sample components. ESD withstand voltages of the sample components are detected. The relation between the ESD withstand voltages and the electrostatic discharge rates are recorded to a database. The testing ESD voltage is imposed on the semiconductor element for testing an ESD decay rate of the semiconductor element. The database is looked up according to the ESD decay rate of the semiconductor element to determine an ESD withstand voltage of the semiconductor element.

A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.

Systems, devices, and methods for characterizing semiconductor devices and thin film materials. The device consists of multiple probe tips that are integrated on a single substrate. The layout of the probe tips could be designed to match specific patterns on a CMOS chip or sample. The device provides for detailed studies of transport mechanisms in thin film materials and semiconductor devices.

A method of monitoring a condition of a SiC MOSFET can include (a) applying a first test gate-source voltage across a gate-source of a SiC MOSFET in-situ, the first test gate-source voltage configured to operate the SiC MOSFET in saturation mode to generate a first drain current in the SiC MOSFET, (b) applying a second test gate-source voltage across the gate-source of the SiC MOSFET in-situ, the second test gate-source voltage configured to operate the SiC MOSFET in fully-on mode to generate a second drain current in the SiC MOSFET, (c) determining a drain-source saturation resistance using the first drain current to provide an indication of a degradation of a gate oxide of the SiC MOSFET; and (d) determining a drain-source on resistance using the second drain current to provide an indication of a degradation of contact resistance of the SiC MOSFET.

An electronic device has a sealing part 90, a first main terminal 11 protruding outward from the sealing part 90, a second main terminal 12 protruding outwardly from the sealing part, an electronic element 95 provided in the sealing part and having a front surface electrically connected to the first main terminal 11 and a back surface electrically connected to the second main terminal 12, a head part 40 connected to the front surface of the electronic element 95, a sensing terminal 13 protruding to an outside from the sealing part 90 and used for sensing and a connection part 35 integrally formed with the head part 40 and electrically connected to the sensing terminal 13. A current flowing through the sensing terminal 13 and the connection part 35 among a sensing current path does not overlap a main current path flowing through the second main terminal 12, the electronic element 95 and the first main terminal 11.

Provided are a semiconductor device and a method of operating the same. A semiconductor includes a test circuit which comprises: a test transistor to be tested for time-dependent dielectric breakdown (TDDB) characteristics using a stress voltage; an input switch disposed between a voltage application node to which the stress voltage is applied and an input node which transmits the stress voltage to the test transistor; and a protection switch disposed between the input node and a ground node.

A portion of a source pad is exposed in an opening of a passivation film. In the exposed portion of the source pad, a wiring region in which a package wiring member is to be bonded and a probe region that is a region different from the wiring region are provided. The probe region has a probe mark of a probe for an energization inspection. An area of the probe mark that overlaps the wiring region is at most 30% of an entire area of the wiring region in a plan view of the silicon carbide semiconductor device.

A method of testing a semiconductor device may include preparing a semiconductor substrate in which the semiconductor substrate includes a test element group including first and second test circuits, measuring first and second leakage currents in the first and second test circuits, respectively, and calculating leakage components by comparing the first and second leakage currents. Each of the first and second test circuits may include an active region, which is an upper portion of the semiconductor substrate, a gate electrode, which is configured to cross the active region and to extend in a first direction, and an active contact, which is on the active region, is spaced apart from the gate electrode, and extends in the first direction. The second test circuit may further include a first gate contact that is connected to the gate electrode and overlaps the active region in a vertical direction perpendicular to the substrate.

In a method of inspecting an error, a lower wiring structure may be formed. A main dummy pattern and a test dummy pattern may be formed on the lower wiring structure, The main dummy pattern may include a via pattern and a wiring pattern having a width greater than a width of the via pattern. The test dummy pattern may be spaced apart from the main dummy pattern by no less than a critical distance. The test dummy pattern may have a width substantially the same as that of the via pattern. The test dummy pattern may have a height substantially the same as that of the main dummy pattern. The test dummy pattern may then be tested to predict an error of the main dummy pattern based on an error of the test dummy pattern.