A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.

A microelectromechanical gyroscope which comprises one or more Coriolis masses driven by a drive transducer and a force-feedback system. The force-feedback circuit comprises first and second sideband modulators and the self-test circuit comprises first and second sideband demodulators.

A semiconductor substrate in includes a buffer layer and a first crystalline layer. A bandgap of the first crystalline layer is smaller than a bandgap of a second layer. When a semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer. With a first electrode and a second electrode provided and a third electrode provided, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed.

Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.

Provided is a technique for enhancing the accuracy of deterioration diagnosis in a semiconductor device. The semiconductor device relating to the technique disclosed in the present specification is provided with a case, a semiconductor chip inside the case, a metal wire bonded to an upper surface of the semiconductor chip, at least one test piece inside the case, and a pair of terminals provided outside the case and connected to the test piece. The test piece is separated from the metal wire inside the case.

A layout for a vertical-cavity surface-emitting laser (VCSEL) is provided. In an example embodiment, the layout comprises a VCSEL, an etched shape around a mesa of the VCSEL, a signal contact layer deposited on section of the mesa, and a ground contact layer. The ground contact layer comprises three parts and is positioned around a first section of the etched shape. The first part of the ground contact layer is deposited on a second section of the etched shape. The second and third parts of the ground contact layer comprise two legs off of the first part. The two legs are symmetrically positioned about two sides of the signal contact layer to form a ground-signal-ground configuration.

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

Disclosed is a device for testing components under elevated pressure in which a pressure chamber is provided. The lateral boundary of the pressure chamber included a ring and an annular part, which may move perpendicularly to the plane of the component to be tested. A velvet-like lining is provided on the end face of the annular part or of the ring that faces the component to be tested. The fibers of the lining protrude from the annular part or from the ring toward the component to be tested and bridge the gap between the device and the component.

The embodiments of the present disclosure provide a semiconductor base plate and a test method thereof. When a first test line and a second test line in the semiconductor base plate are tested, a resistivity of the first test line can be tested by directly loading voltages to a first test pad and a second test pad after a first conductive layer is formed and before a first insulating layer is formed. After a second conductive layer is formed, a resistivity of the second test line is tested by loading voltages to a third test pad and a fourth test pad.

A device having at least one power semiconductor die coated with a metallization and at least one light guide having two opposite ends. The first end is able to be connected at least to a light source and to a light receiver. The second end is permanently fixed facing to a surface of the metallization such that to form a light path towards said surface and a light path from said surface.