This disclosure describes an elastic multi-contact probe that includes conductive strips each of which comprises a conductive elastomer; dielectric strips formed on a back surface of a respective conductive strip; and a layer of a thermoplastic formed on back surfaces of the dielectric strips. The disclosure also describes a method that includes measuring a first I-V curve between a pair of inner probes of the an elastic multi-contact probe based on a first current applied to a pair of outer probes; determining a first slope of a linear region of the first I-V curve; measuring a second I-V curve between the pair of inner probes based on a second current applied to the pair of inner probes; determining a second slope of a linear region of the second I-V curve; and calculating a sheet resistance and a contact resistivity of the semiconductor material based on the first and second slopes.

Provided is a method of measuring the Fe concentration in a p-type silicon wafer by the SPV method, by which the detection limit for the Fe concentration can be lowered, and the measurement can be performed in a short time. The measurement by the SPV method is performed in a measurement mode in which irradiation with a plurality of lights having mutually different wavelengths is performed during the same period under conditions where (i) Time Between Readings is 35 ms or more and 120 ms or less and Time Constant is 20 ms or more, or Time Between Readings is 10 ms or more and less than 35 ms and Time Constant is 100 ms or more, and (ii) Number of Readings is 12 times or less.

A system, method and apparatus for measuring carrier lifetime of a device comprises subjecting a test device to a voltage via a voltage source associated with the test system, disconnecting the test device from the voltage source, measuring the voltage as a function of time, measuring the current as a function of time, and determining a carrier lifetime of the test piece according to the slope of the measured voltage and the measured current.

A structure for testing a semiconductor device. A first resistor structure (R1) comprises a first active region (110) and a first polysilicon gate (130) disposed on the first active region (110); the width of the first active region (110) is greater than a predetermined width value; the predetermined width value is the critical value of the width of an active region of the semiconductor device when the step height of a shallow trench isolation structure of the semiconductor device affects the width of a polysilicon gate; the design width of the first polysilicon gate (130) is identical to that of the polysilicon gate of the semiconductor device; a second resistor structure (R2) is connected to the first resistor structure (R1) according to a predetermined circuit structure to form a test circuit, and comprises a second active region (210) and a second polysilicon gate (230) disposed on the second active region (210); the width of the second active region (210) is less than the predetermined width value; the design size of the second polysilicon gate (230) is identical to that of the first polysilicon gate (130); the total resistance of a branch circuit where the second resistor structure (R2) is located is equal to the total resistance of a branch circuit where the first resistor structure (R1) is located.

Methods, tools and systems for full characterization of thin and ultra-thin layers employed in advanced semiconductor device structures are disclosed.

Methods and systems for determining band structure characteristics of high-k dielectric films deposited over a substrate based on spectral response data are presented. High throughput spectrometers are utilized to quickly measure semiconductor wafers early in the manufacturing process. Optical models of semiconductor structures capable of accurate characterization of defects in high-K dielectric layers and embedded nanostructures are presented. In one example, the optical dispersion model includes a continuous Cody-Lorentz model having continuous first derivatives that is sensitive to a band gap of a layer of the unfinished, multi-layer semiconductor wafer. These models quickly and accurately represent experimental results in a physically meaningful manner. The model parameter values can be subsequently used to gain insight and control over a manufacturing process.

A probe for direct nano- and micro-scale electrical characterization of materials and semi conductor wafers. The probe (10) comprises a probe body (12), a first cantilever (20a) extending from the probe body. The first cantilever defining a first loop with respect to said probe body. The probe further comprises a first contact probe being supported by said first cantilever, and a second contact probe being electrically insulated from the first contact probe. The second contact probe being supported by the first cantilever or by a second cantilever (20b) extending from the probe body.

A semiconductor device, its manufacturing method, and a radiation measurement method are presented, relating to semiconductor techniques. The semiconductor device includes: a substrate comprising a base area and a collector area adjacent to each other; a plurality of semiconductor fins on the substrate, wherein the plurality of semiconductor fins comprises at least a first semiconductor fin and a second semiconductor fin on the base area and separated from each other, the first semiconductor fin comprises an emission area adjacent to the base area, and the second semiconductor fin comprises a first region adjacent to the base area; a first gate structure on the second semiconductor fin; and a first source and a first drain at two opposite sides of the first gate structure and at least partially in the first region. Radiation in a semiconductor apparatus can be measured through this semiconductor device.

The method is a method of evaluating a manufacturing process of a silicon material, wherein the manufacturing process includes a process that uses a member containing a carbon-containing sintered body, and the method of evaluating the manufacturing process of a silicon material includes performing DLTS measurement on a silicon material manufactured in the manufacturing process, and estimating a heavy metal contamination source of a silicon material manufactured in the manufacturing process with an indicator in the form of presence/absence of detection of a peak of a carbon-related level and presence/absence of detection of a peak of a heavy metal-related level in a DLTS spectrum obtained by the DLTS measurement.

A measurement apparatus for measuring dimensions within a semiconductor device includes an illumination source configured to direct light onto a stage configured to hold the semiconductor device, and a detection assembly configured to receive light diffracted by the semiconductor device, in which the detection assembly includes a detector configured to receive light diffracted by the semiconductor device and determine a measurement of a periodic structure within the semiconductor device based on the received diffracted light, and a diffraction pattern filter configured to permit light diffracted by the periodic structure to be measured to reach the detector and block at least a portion of light diffracted by other structures in the semiconductor device from reaching the detector. Embodiments include methods of measuring a semiconductor device using the measurement apparatus and methods of making the diffraction pattern filter.