An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

Devices and methods are provided, which detect a short circuit condition related to a semiconductor switch. A short circuit condition may be determined when a control signal of the switch exceeds a first reference, and a change of load current of the switch exceeds a second reference.

Devices and methods are provided, which detect a short circuit condition related to a semiconductor switch. A short circuit condition may be determined when a control signal of the switch exceeds a first reference, and a change of load current of the switch exceeds a second reference.

In one embodiment, the method is configured for producing optoelectronic semiconductor components (1) and includes the steps of: providing a leadframe assembly (20) with a multiplicity of leadframes (2), each having at least two leadframe parts (21, 22); forming at least a part of the leadframe assembly (20) with a housing material for housing bodies (4); dividing the leadframe assembly (20) between at least one part of the columns (C) and/or the rows (R), wherein the leadframes (2) remain arranged in a matrix-like manner; equipping the leadframes (2) with at least one optoelectronic semiconductor chip (3); testing at least one part of the leadframes (2) equipped with the semiconductor chips (3) and formed with the housing material after the step of dividing; and separating to form the semiconductor components (1) after the step of forming and after the step of testing.

Disclosed is an integrated circuit (1) including two electrical power supply terminals (2a, 2b), respectively positive and ground, forming part of a first electrical power supply system (2) internal to the integrated circuit and providing its electrical power supply using an electrical power supply source external to the integrated circuit. The integrated circuit includes two pins (3a, 3b), respectively positive and ground, forming part of a second electrical power supply system (3) and providing an auxiliary electrical connection of the integrated circuit with the outside, the second power supply system being in parallel with the first power supply system, the first power supply system being open when the second power supply system is closed and vice versa.

A contact position of a probe needle with respect to electrode pads 71 to 75 of a semiconductor device is inspected in advance when performing an inspection by a prober on the semiconductor device formed on a wafer W placed on a stage 11. A reticle 31 on which shapes 61 to 65 indicating positions of the probe needles are formed is placed instead of the probe needles at a position where the probe needles are arranged. The semiconductor device formed on the wafer W is imaged by the imaging unit 33 through the reticle 31. A positional relationship between the shapes formed on the reticle 31 and the electrode pads 71 to 75 is analyzed from the image. When necessary, a position of the stage 11 is adjusted such that centers of the shapes 61 to 65 and centers of the electrode pad 71 to 75 are coincident.

A contact position of a probe needle with respect to electrode pads 71 to 75 of a semiconductor device is inspected in advance when performing an inspection by a prober on the semiconductor device formed on a wafer W placed on a stage 11. A reticle 31 on which shapes 61 to 65 indicating positions of the probe needles are formed is placed instead of the probe needles at a position where the probe needles are arranged. The semiconductor device formed on the wafer W is imaged by the imaging unit 33 through the reticle 31. A positional relationship between the shapes formed on the reticle 31 and the electrode pads 71 to 75 is analyzed from the image. When necessary, a position of the stage 11 is adjusted such that centers of the shapes 61 to 65 and centers of the electrode pad 71 to 75 are coincident.

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

To provide a measurement device which allows long-term accurate measurement of voltage without adversely affecting a device under test, by ensuring a predetermined level of resistance to ESD and reducing leakage current. A measurement device includes a probe needle for contacting a device under test, a first FET for detecting voltage of the device under test, and a protection circuit for protecting the first FET from static electricity. The protection circuit includes a second FET having an oxide semiconductor film as a channel formation region.