System and method, in the field of device control, for detecting and processing one or more deviations from an acceptable electrical behavior in an electrical device are provided here. The system may include a sampling unit for receiving at least one activity indication, a storage to store acceptable values related to the acceptable electrical behavior, an active time measurement unit to receive the activity indication and measure an active time duration, an inactive time measurement unit to receive the activity indication and measure an inactive time duration and a deviation processor to compute values derived from the activity indication, the active time duration and the inactive time duration, detect and analyze one or more deviations between the acceptable values and the derived values.

Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

During frequency detection, a constant current source outputs an output current to charge a variable capacitor for multi-period. In a calibration mode, according to a comparison result between a cross voltage of the variable capacitor and a reference voltage, a capacitance value of the variable capacitor is adjusted. In a monitor mode, according to a reference frequency and the cross voltage of the variable capacitor, a frequency under test of a circuit under test is detected.

A device may determine an analog gain for an aggregated analog signal. The aggregated analog signal may be associated with a calibration test to be used to determine a set of calibration parameters for a load test of a base station. The device may determine the set of calibration parameters for the load test based on an outcome of performing a calibration test. The set of calibration parameters may result in a set of digital gains approximately centered in a digital dynamic gain range. The device may perform the load test after determining the analog gain for the analog signal and based on the set of calibration parameters for the load test.

Systems are provided for cable length measurement in a communication system. The systems include a transmitter, a receiver, a signal sampler and a cable length calculation unit. The transmitter is configured to transmit a plurality of data symbols at a first data rate via a wired data communication link, and the receiver is configured to receive a reflection signal. The signal sampler is configured to sample the received reflection signal using a phase shift number of shifting sampling phases to generate reflection samples, and combine the reflection samples with different sampling phases to generate a series of reflection samples corresponding to a second data rate higher than the first data rate. The cable length calculation unit is configured to determine a delay parameter from the series of reflection samples, and generate an estimate of a length of the data communication link.

A radio-frequency receiver includes built-in-self-test (BIST) circuitry which generates a self-test signal. A local oscillator signal is divided. A self-test oscillation signal is generated, based, at least in part, on the frequency-divided local oscillation signal. The self-test signal is generated based on the self-test oscillation signal. The BIST circuitry includes a divider, which divides the self-test oscillation signal. The frequency-divided local oscillation signal and the divided self-test oscillation signal are used to perform one or more of generating the self-test oscillation signal and controlling the generation of the self-test oscillation signal. The radio-frequency receiver may be an automotive radar receiver.

The disclosed technology generally relates to electrical overstress protection devices, and more particularly to electrical overstress monitoring devices for detecting electrical overstress events in semiconductor devices. In one aspect, a device configured to monitor electrical overstress (EOS) events includes a pair of spaced conductive structures configured to electrically arc in response to an EOS event, wherein the spaced conductive structures are formed of a material and have a shape such that arcing causes a detectable change in shape of the spaced conductive structures, and wherein the device is configured such that the change in shape of the spaced conductive structures is detectable to serve as an EOS monitor.

A device may determine an analog gain for an aggregated analog signal. The aggregated analog signal may be associated with a calibration test to be used to determine a set of calibration parameters for a load test of a base station. The device may determine the set of calibration parameters for the load test based on an outcome of performing a calibration test. The set of calibration parameters may result in a set of digital gains approximately centered in a digital dynamic gain range. The device may perform the load test after determining the analog gain for the analog signal and based on the set of calibration parameters for the load test.

A circuit for detecting failure of a device includes a plurality of monitoring modules. Each respective monitoring module of the plurality of monitoring modules is configured to generate a monitoring value at an output of the respective monitoring module based on a signal received at an input of the respective monitoring module. The circuit further includes a data selector module configured to couple, for each step of a switching cycle, the input of each of the plurality of monitoring modules to one of a plurality of function modules such that each of the plurality of monitoring modules generates the monitoring value for each of the plurality of function modules to generate monitoring information and evaluation logic configured to determine whether a failure has occurred at the plurality of function modules based on the monitoring information.

A test system includes a plurality of test core devices and a plurality of first buses. The plurality of test core devices are electrically connected to a device under test (DUT). The plurality of first buses are electrically connected to the test core devices, where at least one set of test core devices selected from the plurality of test core devices are merged to be a merged test core device through one or more of the plurality of first buses.