A stacked semiconductor device may include: a base die; and a plurality of core dies stacked over the base die and coupled to each other through a plurality of through-electrodes and a reference through-electrode, wherein the base die includes a first test circuit suitable for transferring a test oscillating signal to at least one target through-electrode among the through-electrodes, and outputting a test output signal by comparing a test base signal generated based on the test oscillating signal, with a test core signal transferred through the reference through-electrode, during a test operation; and wherein each of the core dies includes a second test circuit suitable for generating the test core signal corresponding to the test oscillating signal transferred through the target through-electrode, and transferring the test core signal to the reference through-electrode, during the test operation.

Methods, systems, and apparatus for testing semiconductor devices.

Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.

A method and apparatus for controlling a tester, related medium and electronic device are provided. The apparatus includes a vibration data collector attached on a side wall of the tester to collect vibration data from the tester during operation thereof. The method includes: receiving the vibration data collected by the vibration data collector; comparing the vibration data with a predetermined threshold to generate a comparison result; and controlling an operating state of the tester based on the comparison result. This method may timely identify any instability of the tester and prompt for repair if necessary. It substantially reduces the time and material costs associated with a test, and thus reduces the non-chip-attributable defect rate.

A semiconductor device includes a control signal generation circuit configured to shift a test mode signal in response to a clock signal to generate a plurality of control signals, and a plurality of temperature sensing circuits each including a first resistor having a resistance that varies depending on temperature and configured to generate a temperature sensing signal based on the resistance in response to a corresponding control signal of the plurality of control signals.

A sensor integrated circuit including a regulator for generating a regulated voltage includes a digital load configured to draw a load current from the regulator in response to a clock signal during in situ operation and a comparator configured to determine the absence or presence of a fault during in situ operation. The load current is less than or equal to a predetermined level in the absence of a fault and is greater than the predetermined level in the presence of a fault. The comparator is responsive to the load current and to a threshold level and is configured to generate a comparator output signal having a level indicative of whether the load current is less than or greater than the threshold level in order to thereby determine the absence or presence of a fault during in situ operation, respectively.

A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.

A measurement system of a device under test (DUT) includes a reference clock synthesizer configured to generate a master reference clock signal, a transmitter unit connected to the reference clock synthesizer and configured to connect to the DUT, and a measurement control system connected to the transmitter unit and configured to control the transmitter unit to generate a test signal pattern based on a first reference clock signal derived from the master reference clock signal, and generate a signal for passing through the DUT based on the test signal pattern. A receiver unit connected to the reference clock synthesizer is configured to connect to the DUT and to detect the signal and generate a digital signal based on the signal and a second reference clock signal derived from the master reference clock signal. The measurement control system is configured to provide an output signal based on the digital signal.

A system, apparatus, and method of testing a plurality of test circuits is disclosed that includes inputting experiment data to the plurality of test circuits; applying a control signal to each of the plurality of test circuits to control application of the experiment data to the plurality of test circuits; and shifting the control signal in response to applying the control signal to each of the plurality of test circuits so that a different bit of the control signal is applied to each of the plurality of test circuits. The method in an aspect further comprises reading out a data out signal from each of the plurality of test circuits; and shifting the data out signal in response to reading out the data out signal from each of the plurality of test circuits.

An integrated circuit includes intellectual property (IP) processing circuitries each including a separate, respective at least one scan chain, and temperature management controller circuitry configured to transmit an input pattern including a plurality of bits to at least one scan chain of a first IP processing circuitry among the IP processing circuitries, detect a temperature of the first IP processing circuitries based on an output pattern received from the at least one scan chain in response to the input pattern being transmitted to the at least one scan chain of the first IP processing circuitry, and control at least one of an operation frequency or an operation voltage of the first IP processing circuitry based on the detected temperature of the first IP processing circuitry.