Device for checking the integrity of a digital transmission for an analog output of a system. The analog output may be checked for transient errors that can be attributed to a digital transmission path embedded somewhere within the vehicle system. A test signal is introduced into a digital transmission that can be reassembled from an analog path of the analog output, and, if not, allows the test device to pinpoint that errors are appearing due to the digital path, and not because of the analog output. In this way, debugging an installation of a system becomes easier; obtaining confidence in reliability of a mixed analog and digital system becomes less of a challenge and less time consuming.

A semiconductor device of an embodiment includes a main circuit configured to perform a predetermined operation to an input signal to output an output signal, an inverse operation circuit configured to receive the output signal of the main circuit as an input, and perform an inverse operation of the predetermined operation by using the output signal to output an inverse operation result signal, and a comparison circuit configured to compare the input signal and the inverse operation result signal, and output a predetermined signal when the input signal and the inverse operation result signal do not coincide with each other.

An integrated circuit (IC) includes: a first functional analog pin or pad; a first analog test bus coupled to the first functional analog pin or pad; first and second analog circuits coupled to the first analog test bus; and a test controller configured to: when the IC is in a functional operating mode, connect an input or output of the first analog circuit to the first analog test bus so that the input or output of the first analog circuit is accessible by the first functional analog pin or pad, and keep disconnected an input or output of the second analog circuit from the first analog test bus, and when the IC is in a test mode, selectively connect the input or output of the first and second analog circuits to the first analog test bus to test the first and second analog circuits using the first analog test bus.

A debug probe (102) for controlling debugging of a target system (104) is described, the debug probe comprising an interface (128) comprising a plurality of pins (202), debug control circuitry (130) to control debugging of the target system based on a digitally sampled level of at least one signal communicated through at least one of the plurality of pins, and measurement circuitry (204) to make a measurement of a property of the target system based on an analogue level of a signal received through said at least one of the plurality of pins.

The present invention is a process by which an engineer can provide as input the design, functional verification goals, and other abstract design details, and receive as output an agent which can be integrated into traditional test benches and will generate stimuli to automatically hit the functional coverage goals for the design. The present invention may employ a system which includes a learning configurator, a pre-trained learning test generator, and a test bench. The pre-trained learning test generator is communicatively coupled to the generator and notably comprises a learning algorithm.

An automated test equipment for testing devices under test is configured to combine different output signals from multiple pins of a single device under test or from pins of a plurality of devices under test to obtain a combined signal; and to extract individual signals or properties of the individual signals from the combined signal.

A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

An electronic circuit includes a ramp signal generator, an oscillator, a monitoring circuit and a logic controller. The ramp signal generator generates a ramp signal. The oscillator generates a clock signal. The monitoring circuit operates in an operation mode selected from a first mode of monitoring an external output voltage and a second mode of performing an analog built-in self-test (ABIST), and generates a comparator output. The logic controller controls the monitoring circuit to operate in the operation mode. When the monitoring circuit operates in the second mode, the logic controller counts the clock signal, controls the monitoring circuit to perform the ABIST based on the ramp signal, and generates an ABIST output indicating whether the monitoring circuit operates normally based on a value of the counting and the comparator output.

An electrical circuit for testing primary internal signals of an ASIC. Only test pin is provided via which a selection can be made of a digital or analog signal to be observed. The electrical circuit includes a Schmitt trigger between the test pin and an output terminal of the electrical circuit. A test mode id activated when a switching threshold of the Schmitt trigger is exceeded. At least one sub-circuit is provided for the observation of a digital signal, having a resistor, an NMOS transistor, and an AND gate, at whose first input the digital signal is present. The resistor is between the test pin and the drain terminal of the NMOS transistor. The source terminal is connected to ground, and the gate terminal is connected to the output of the AND gate. The second input of the AND gate being connected to the output terminal of the electrical circuit.