A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.

A display device includes pixels electrically connected to a plurality of scan lines and a plurality of data lines, respectively, a scan driver that provides a scan signal to each of the plurality of scan lines, a voltage supply that supplies a first gate voltage to the scan driver through a first gate power line, and a voltage compensator. The voltage compensator senses a partial voltage of the first gate voltage applied to the scan driver through a feedback line. The voltage compensator compensates the first gate voltage with a second gate voltage in case that the sensed first gate voltage is greater than a first reference voltage.

A power management system includes a direct current-direct current DC-DC conversion circuit, a first control circuit, a charging circuit, an input port, and an output port. The input port is configured to receive an input voltage. The output port is configured to supply an output voltage to a load. The DC-DC conversion circuit is configured to charge the output port from the input port, to adjust the output voltage. The first control circuit is configured to: obtain a second feedback voltage of the output voltage from the output port, generate a first control signal based on the second feedback voltage and a second reference signal, and supply the first control signal to the charging circuit. The charging circuit charges the output port from the input port based on the first control signal, to supplementally adjust the output voltage.

An electronic device is provided. The electronic device includes a first power management integrated circuit (PMIC) with a first fault controller connected to a first node and a first interface circuit connected to a second node; a second PMIC with a second fault controller connected to the first node and a second interface circuit connected to the second node; and a third PMIC with a third fault controller connected to the first node and a third interface circuit connected to the second node. The first fault controller is configured to, during a power on sequence or a power off sequence, detect a change in a voltage level of the first node. The first interface circuit is configured to communicate with any one or any combination of the second interface circuit and communication and the third interface circuit based on the change in the voltage level of the first node.

An electronic device is provided. The electronic device includes a first power management integrated circuit (PMIC) with a first fault controller connected to a first node and a first interface circuit connected to a second node; a second PMIC with a second fault controller connected to the first node and a second interface circuit connected to the second node; and a third PMIC with a third fault controller connected to the first node and a third interface circuit connected to the second node. The first fault controller is configured to, during a power on sequence or a power off sequence, detect a change in a voltage level of the first node. The first interface circuit is configured to communicate with any one or any combination of the second interface circuit and communication and the third interface circuit based on the change in the voltage level of the first node.

Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

A smart circuit breaker may provide a smart-circuit-breaker power monitoring signal that includes information about power consumption of devices connected to the smart circuit breaker. The smart-circuit-breaker power monitoring signal may be used in conjunction with power monitoring signals from the electrical mains of the building for providing information about the operation of devices in the building. For example, the power monitoring signals may be used to (i) determine the main of the house that provides power to the smart circuit breaker, (ii) identify devices receiving power from the smart circuit breaker, (iii) improve the accuracy of identifying device state changes, and (iv) train mathematical models for identifying devices and device state changes.

Techniques are provided for detecting a fault across a pair of lines. Pulse power is applied across the pair of lines. The pulse power comprises alternating pulse on-time intervals and pulse off-time intervals. During a pulse off-time interval, a resistor is connected across the pair of lines and then disconnected when a voltage across the pair of lines reaches a first droop percentage in a first period of time. After disconnecting the resistor, it is determined whether the voltage across the pair of lines droops at least a second droop percentage within a second period of time that begins after the first period of time. Occurrence of a line-to-line fault across the pair of lines is determined when the voltage across the pair of lines droops by at least the second droop percentage or more within the second period of time.

A power delivery system for a computing device includes a power connector, a power delivery switch, a charging circuit, and a hardware controller. The power connector is configured to selectively electrically connect with a power supply unit. The power delivery switch is electrically intermediate the power connector and the charging circuit. The hardware controller is configured to limit a charging current at the charging circuit to a sub-threshold level for a current-limiting duration based at least on initiation of a transition of the power delivery switch from an OFF state to an ON state that lasts for a switching duration that is less than the current-limiting duration. The charging circuit is configured to modulate the charging current to a regulated charging current and deliver the regulated charging current to a system load of the computing device after the current-limiting duration has elapsed.

A power delivery system for a computing device includes a power connector, a power delivery switch, a charging circuit, and a hardware controller. The power connector is configured to selectively electrically connect with a power supply unit. The power delivery switch is electrically intermediate the power connector and the charging circuit. The hardware controller is configured to limit a charging current at the charging circuit to a sub-threshold level for a current-limiting duration based at least on initiation of a transition of the power delivery switch from an OFF state to an ON state that lasts for a switching duration that is less than the current-limiting duration. The charging circuit is configured to modulate the charging current to a regulated charging current and deliver the regulated charging current to a system load of the computing device after the current-limiting duration has elapsed.