G06F7/24

Storing data and parity via a computing system
11609912 · 2023-03-21 · ·

A method includes generating a plurality of parity blocks from a plurality of lines of data blocks. The plurality of lines of data blocks are stored in data sections of memory of a cluster of computing devices of the computing system by distributing storage of individual data blocks of the plurality of lines of data blocks among unique data sections of the cluster of computing devices. The plurality of parity blocks are stored in parity sections of memory of the cluster of computing devices by distributing storage of parity blocks of the plurality of parity blocks among unique parity sections of the cluster of computing devices.

Storing data and parity via a computing system
11609912 · 2023-03-21 · ·

A method includes generating a plurality of parity blocks from a plurality of lines of data blocks. The plurality of lines of data blocks are stored in data sections of memory of a cluster of computing devices of the computing system by distributing storage of individual data blocks of the plurality of lines of data blocks among unique data sections of the cluster of computing devices. The plurality of parity blocks are stored in parity sections of memory of the cluster of computing devices by distributing storage of parity blocks of the plurality of parity blocks among unique parity sections of the cluster of computing devices.

METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MULTIPLICATION
20230085048 · 2023-03-16 ·

A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.

METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MULTIPLICATION
20230085048 · 2023-03-16 ·

A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.

Secret table reference system, method, secret calculation apparatus and program

A secure table reference system includes a first combining part 11.sub.n for generating [v′] of v′ ∈ F.sup.m+nt in which d and v are combined, a difference calculation part 12.sub.n for generating [r″] of r″ that has a difference between a certain element of r and an element before the certain element as an element corresponding to the certain element, a second combining part 13.sub.n for generating [r′] of r′ ∈ F.sup.m+nt in which r″ and an m-dimensional zero are combined, a permutation calculation part 14.sub.n for generating {{σ}} of a permutation σ that stably sorts v′ in ascending order, a permutation application part 15.sub.n for generating [s] of s: =σ(r′) obtained by applying the permutation σ to r′, a vector generation part 16.sub.n for generating [s′] of a prefix-sum s′ of s, an inverse permutation application part for generating [s″] of s″ obtained by applying an inverse permutation σ.sup.−1 of the permutation σ to s′, and an output part 17.sub.n for generating [x] of x ∈ F.sup.m consisting of (n.sub.t+1)th and subsequent elements of s″.

Secret table reference system, method, secret calculation apparatus and program

A secure table reference system includes a first combining part 11.sub.n for generating [v′] of v′ ∈ F.sup.m+nt in which d and v are combined, a difference calculation part 12.sub.n for generating [r″] of r″ that has a difference between a certain element of r and an element before the certain element as an element corresponding to the certain element, a second combining part 13.sub.n for generating [r′] of r′ ∈ F.sup.m+nt in which r″ and an m-dimensional zero are combined, a permutation calculation part 14.sub.n for generating {{σ}} of a permutation σ that stably sorts v′ in ascending order, a permutation application part 15.sub.n for generating [s] of s: =σ(r′) obtained by applying the permutation σ to r′, a vector generation part 16.sub.n for generating [s′] of a prefix-sum s′ of s, an inverse permutation application part for generating [s″] of s″ obtained by applying an inverse permutation σ.sup.−1 of the permutation σ to s′, and an output part 17.sub.n for generating [x] of x ∈ F.sup.m consisting of (n.sub.t+1)th and subsequent elements of s″.

DYNAMIC AUGMENTING OF RELEVANCE RANKINGS USING DATA FROM EXTERNAL RATINGS SOURCES

In general, embodiments of the present invention provide systems, methods and computer readable media for dynamically augmenting relevance rankings using data from external ratings sources.

Signal processing apparatus, method, program, and recording medium
11604852 · 2023-03-14 · ·

A signal processing apparatus comprises an operation processing part that performs operation processing on data represented in the two's complement representation and a storage processing part that performs storage processing on data represented in a second representation format as a data representation format, and in the second representation format, a data value is identical to one in the two's complement representation when the value is positive or zero, and all the bits lower than the most significant bit that indicates the sign in the two's complement representation are inverted when a data value is negative.

Signal processing apparatus, method, program, and recording medium
11604852 · 2023-03-14 · ·

A signal processing apparatus comprises an operation processing part that performs operation processing on data represented in the two's complement representation and a storage processing part that performs storage processing on data represented in a second representation format as a data representation format, and in the second representation format, a data value is identical to one in the two's complement representation when the value is positive or zero, and all the bits lower than the most significant bit that indicates the sign in the two's complement representation are inverted when a data value is negative.

Sorting networks using unary processing

Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.