The present disclosure relates to an emulation test system for flash translation layer and a method thereof, the system comprising a network block device, a virtual hardware accelerator, a flash translation layer module, and a virtual flash memory based on the network block device, wherein the network block device is configured to receive and forward test information, the test information including a read instruction and/or a write instruction and data to be written; the virtual hardware accelerator is configured to allocate the test information to each thread of the virtual hardware accelerator and perform virtual hardware acceleration on the flash translation layer module; and the flash translation layer module is configured to operate the virtual flash memory based on the test information to obtain an operation result.

In an approach, a processor receives an input indicative of a set of registers, the set of registers being configured for obtaining output data from a design-under-test (DUT) in a field-programmable gate array (FPGA) module. A processor executes a set of instructions for monitoring the output data in the set of registers;. A processor generates data indicative of at least one portion of changes of the output data in the set of registers during the execution of the set of instructions. A processor causes a separate machine to analyze the data via utilizing an interface to send the data to the separate machine.

A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

A method for monitoring an operation condition of an interactive information system is provided. The interactive information system includes a touch panel and a touch control unit, and executes a resident scanning program to detect whether a hardware-related issue or a software-related issue of the touch panel or the touch control unit has occurred. When the hardware-related issue has occurred, the interactive information system downloads and executes a hardware diagnosis program to obtain a diagnosis result. When the software-related issue has occurred, the interactive information system downloads and executes a software adjustment program to resolve the software-related issue.

A method for monitoring an operation condition of an interactive information system is provided. The interactive information system includes a touch panel and a touch control unit, and executes a resident scanning program to detect whether a hardware-related issue or a software-related issue of the touch panel or the touch control unit has occurred. When the hardware-related issue has occurred, the interactive information system downloads and executes a hardware diagnosis program to obtain a diagnosis result. When the software-related issue has occurred, the interactive information system downloads and executes a software adjustment program to resolve the software-related issue.

A variable power bus (VPB) cable, such as a USB Type-C cable, is validated for actual current capacity with respect to a specified power rating for the cable. The power cable validation is performed when the cable is connected to a power storage adapter and a portable information handling system. The validation includes, prior to negotiating a power delivery contract for electrical power to be supplied to the information handling system from the VPB port via the VPB cable, applying a first voltage to the VPB cable to identify a first indication of a current capacity of the VPB cable; and when the first indication confirms that the current capacity of the VPB cable corresponds to a specified power rating for the VPB cable, enabling the power delivery contract to be negotiated according to the specified power rating, otherwise blocking the power delivery contract using the VPB cable.

Techniques described herein relate to a method for performing testing operations for information handling systems. The method includes obtaining a test case from an information handling system; in response to obtaining the test case: obtaining log information associated with the test case from the information handling system; performing data preparation to generate processed subsequences using the log information; applying a plurality of prediction models to the processed subsequences and training data to generate anomalous subsequence predictions; generating ensemble anomaly scores and severity indexes associated with the processed subsequences using the anomalous subsequence predictions and the processed subsequences; making a determination that the ensemble anomaly scores and severity indexes associated with the processed subsequences result in detection of an anomalous subsequence; and in response to the determination: determining a next best test case associated with the anomalous subsequence; and initiating performance of the next best test case.

Techniques described herein relate to a method for performing testing operations for information handling systems. The method includes obtaining a test case from an information handling system; in response to obtaining the test case: obtaining log information associated with the test case from the information handling system; performing data preparation to generate processed subsequences using the log information; applying a plurality of prediction models to the processed subsequences and training data to generate anomalous subsequence predictions; generating ensemble anomaly scores and severity indexes associated with the processed subsequences using the anomalous subsequence predictions and the processed subsequences; making a determination that the ensemble anomaly scores and severity indexes associated with the processed subsequences result in detection of an anomalous subsequence; and in response to the determination: determining a next best test case associated with the anomalous subsequence; and initiating performance of the next best test case.

In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.