Systems and techniques that facilitate quantum circuit valuation are provided. In various embodiments, a system can comprise an input component that can access a first quantum circuit. In various embodiments, the system can further comprise a valuation component that can appraise the first quantum circuit based on one or more factors (e.g., frequency factor, complexity factor, resource factor, similarity factor), thereby yielding a value score that characterizes the first quantum circuit. In various instances, the system can further comprise an execution component that can recommend deployment of the first quantum circuit based on determining that the value score exceeds a threshold.

Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

A system and method are provided for simulating circuits that transmit bidirectional signals between some ports using simulators designed originally for electrical circuits and systems, that eliminate the need for different port interfaces. The system and method can be applied to simulate photonic circuits either standalone or integrated with electrical circuits and systems. In one method implemented by the system potential and flow representations, available for example in Verilog-A simulators, are used to create bidirectional signals on a single bus line to transmit optical signals. In another method implemented by the system, the system auto-configures each optical port type as left or right at runtime or during a pre-simulation initialization to allow for bidirectional signals with a single port interface.

A system and method are provided for simulating circuits that transmit bidirectional signals between some ports using simulators designed originally for electrical circuits and systems, that eliminate the need for different port interfaces. The system and method can be applied to simulate photonic circuits either standalone or integrated with electrical circuits and systems. In one method implemented by the system potential and flow representations, available for example in Verilog-A simulators, are used to create bidirectional signals on a single bus line to transmit optical signals. In another method implemented by the system, the system auto-configures each optical port type as left or right at runtime or during a pre-simulation initialization to allow for bidirectional signals with a single port interface.

Disclosed is a method of operating a system-on-chip automatic design device. The system-on-chip automatic design device includes a first synthesizer and a second synthesizer. The method includes generating a first code, based on information of a first signal and information of a second signal that are used in a first IP (Intellectual Property) block, classifying a first signal code corresponding to the first signal and a second signal code corresponding to the second signal from the first code, synthesizing, through the first synthesizer, a first communication architecture configured to transmit the first signal, based on the classified first signal code, and synthesizing, through the second synthesizer, a second communication architecture configured to transmit the second signal based on the classified second signal code.

Disclosed is a method of operating a system-on-chip automatic design device. The system-on-chip automatic design device includes a first synthesizer and a second synthesizer. The method includes generating a first code, based on information of a first signal and information of a second signal that are used in a first IP (Intellectual Property) block, classifying a first signal code corresponding to the first signal and a second signal code corresponding to the second signal from the first code, synthesizing, through the first synthesizer, a first communication architecture configured to transmit the first signal, based on the classified first signal code, and synthesizing, through the second synthesizer, a second communication architecture configured to transmit the second signal based on the classified second signal code.

A method of minimizing a cost function of a quantum computation is provided. The method comprises receiving input of an initial state of a quantum problem instance comprising a Hamiltonian with an associated cost function. The Hamiltonian is converted into a number of Pauli strings, which are used to form an operator pool. The Pauli strings in the operator pool are ranked according to how much they lower a value of the cost function with respect to the initial state. Pauli strings are iteratively added from the operator pool to a parameterized quantum circuit, in a manner to minimize circuit depth, until a variational quantum eigensolver (VQE) algorithm converges to an approximate ground state wave function generated by the parameterized quantum circuit.

A method of minimizing a cost function of a quantum computation is provided. The method comprises receiving input of an initial state of a quantum problem instance comprising a Hamiltonian with an associated cost function. The Hamiltonian is converted into a number of Pauli strings, which are used to form an operator pool. The Pauli strings in the operator pool are ranked according to how much they lower a value of the cost function with respect to the initial state. Pauli strings are iteratively added from the operator pool to a parameterized quantum circuit, in a manner to minimize circuit depth, until a variational quantum eigensolver (VQE) algorithm converges to an approximate ground state wave function generated by the parameterized quantum circuit.

Static and automatic realization of inter-basic block burst transfers for high-level synthesis can include generating an intermediate representation of a design specified in a high-level programming language, wherein the intermediate representation is specified as a control flow graph, and detecting a plurality of basic blocks in the control flow graph. A determination can be made that plurality of basic blocks represent a plurality of consecutive memory accesses. A sequential access object specifying the plurality of consecutive memory accesses of the plurality of basic blocks is generated. A hardware description language (HDL) version of the design is generated, wherein the plurality of consecutive memory accesses are designated in the HDL version for implementation in hardware using a burst mode.

Aspects of the invention include obtaining one or more feature values that define an architecture design of a memory array and implementing a machine learning model to obtain a predicted power, performance, and area (PPA) of the memory array based on the one or more features. The predicted PPA output by the machine leaning model is assessed based on predefined PPA goals. A design of an integrated circuit that includes the memory array is finalized and fabricated based on the predicted PPA meeting the predefined PPA goals.