A method for dependent failure analysis of a circuit design includes obtaining a circuit design comprising a plurality of circuit elements, and generating a first cone of influence and a second cone of influence for the circuit design. The first cone of influence corresponds to a first one or more inputs of the circuit design. The second cone of influence corresponds to a second one or more inputs of the circuit design. The method further includes determining a first shared circuit element of the circuit elements within a first intersection between the first cone of influence and the second cone of influence. Further, the method includes determining a first coupling factor based on the first intersection between the first cone of influence and the second cone of influence, and outputting the first shared circuit element and the first coupling factor to a memory.

Apparatuses, systems, and techniques for designing a data path circuit such as a parallel prefix circuit with reinforcement learning are described. A method can include receiving a first design state of a data path circuit, inputting the first design state of the data path circuit into a machine learning model, and performing reinforcement learning using the machine learning model to output a final design state of the data path circuit, wherein the final design state of the data path circuit has decreased area, power consumption and/or delay as compared to conventionally designed data path circuits.

Failure mode, effects, and diagnostic analysis (FMEDA) is performed on hardware Intellectual Property (IP) of an electronic system. The analysis includes accessing a library of safety library components, each safety library component containing failure mode characterizations and safety data about a hardware model; and compiling the safety library components and the hardware IP. The compiling includes mapping instances of hardware models in the hardware IP to corresponding safety library components and aggregating the characterizations and safety data of the corresponding components.

A computer-implemented method of producing a trained Machine Learning based Task Contention Model to predict time delays resulting from contention between tasks running in parallel on a multi-processor system is provided herein. The method includes: executing a plurality of microbenchmarks, μBenchmarks B.sub.j, on the multi-processor system in isolation and measuring at least one resultant Performance Monitoring Counter, PMC, over time to extract ideal characteristic footprints of each μBenchmark when operating in isolation; executing possible pairing scenarios of the plurality of μBenchmarks in parallel on the multi-processor system and measuring the effect on the execution time of each μBenchmark, ΔT.sup.B.sup.j, resulting from contention over interference channels within the multi-processor system; and training a machine learning model using, as an input, the at least one PMC measure in isolation of each μBenchmark and, at the output, the corresponding ΔT.sup.B.sup.j during the parallel execution of each pairing scenario as training inputs.

This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes. The management process can determine to have the participating processes synchronously transition to another one of the phases or that the participating processes have compiled the circuit design into a compiled design corresponding to the circuit design, and deploy the compiled design in an emulator for verification of a functionality of the electronic device.

This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes. The management process can determine to have the participating processes synchronously transition to another one of the phases or that the participating processes have compiled the circuit design into a compiled design corresponding to the circuit design, and deploy the compiled design in an emulator for verification of a functionality of the electronic device.

In an information processing device according to the present invention, a statistics estimation unit estimates a value of a state quantity by using a statistical model constructed based on values of past state quantities of a target device. A physical estimation unit estimates a value of a state quantity by using a physical model constructed based on design data of the target device. A specification unit specifies a value to be used to manage the target device from the value estimated by the statistics estimation unit and the value estimated by the physical estimation unit based on deterioration of the target device with time.

In an information processing device according to the present invention, a statistics estimation unit estimates a value of a state quantity by using a statistical model constructed based on values of past state quantities of a target device. A physical estimation unit estimates a value of a state quantity by using a physical model constructed based on design data of the target device. A specification unit specifies a value to be used to manage the target device from the value estimated by the statistics estimation unit and the value estimated by the physical estimation unit based on deterioration of the target device with time.

A repository is configured in a hybrid data processing environment comprising a classical computing system and a quantum computing system, to hold a plurality of quantum circuit components (QCC(s)). A degree of difficulty in simulating the received QCC in the classical computing system is transformed into a classical hardness score. A degree of difficulty in implementing the received QCC in the quantum computing system is transformed into a quantum hardness score. A first parameter in a metadata data structure associated with the received QCC is populated with the classical hardness score. A second parameter in the metadata data structure associated with the received QCC is populated with the quantum hardness score. The received QCC is transformed into a library element by at least augmenting the received QCC with the metadata data structure. The library element is added to the repository.

Digital approximate squarer (aSQR)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed aSQR methods can operate asynchronously and or synchronously. For applications where low precisions is acceptable, fewer interpolations can yield less precise square approximation, which can be computed faster and with lower power consumption. Conversely, for applications where higher precision are required, more interpolations steps can generate more precise square approximation. By utilizing the disclosed aSQR method, precision objectives of a squarer approximation function can be programmed real-time and on the fly, which enables optimizing for power consumption and speed of squaring, in addition to optimize for the approximate squarer's die size and cost.