A storage controller of a data storage system maintains, for each interrupt vector, (1) a pending status that indicates whether one or more completions are pending in the completion queue (CQ) associated with the interrupt vector, and (2) an in-progress status that indicates whether or not the storage controller is currently in the process of composing an interrupt. The storage controller utilizes these two statuses to reduce or eliminate spurious interrupts by preventing an interrupt from being composed if there are no completions in the CQ, by preventing an interrupt from being composed if the corresponding interrupt mask has been set before composition of the interrupt begins, and by preventing an interrupt from being sent to the host system in cases where the interrupt mask was set after composition of the interrupt began, but before the interrupt has been sent to the host system.

Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network appliance through a bus system. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are transmitted from the NIC to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing transmission of the received data packets from the NIC to the host CPU for processing.

An adapter module executing on a computing device of a computing environment is to be used to transmit packets from a network interface card of the computing environment to a control program executing within the computing environment. The adapter module obtains packet information of a packet received at the network interface card. Based on obtaining the packet information, a packet completion queue entry is generated in a packet completion queue and the packet information is stored in the packet completion queue entry. The packet information is to be used to locate a data buffer into which the packet is stored. The packet completion queue entry is provided to the control program to be used by the control program to retrieve the packet from the data buffer.

This disclosure provides systems, methods, and devices for image signal processing that support scalable, low latency interrupt handling. In a first aspect, a method of image processing includes receiving, by a controller, an interrupt notification based on a data write into a portion of a memory; determining, by the controller and based on the interrupt notification, a fill level associated with the portion of the memory; and transferring, by the controller and based on the fill level satisfying a threshold level associated with a processor, data associated with the data write to the processor. Other aspects and features are also claimed and described.