An electronic device according to various embodiments may comprise: a sensor circuit; a memory storing handler activation information; and a first processor and a second processor operatively connected to the sensor circuit and the memory. The sensor circuit may be configured to transmit an interrupt signal using an interrupt transmission unit comprising circuitry electrically connected to the first processor and the second processor, and configured to transmit sensor data using a sensor data transceiver electrically connected to the first processor and the second processor. The memory may store instructions which, when executed, cause the first processor to: amend or update interrupt handler activation information in the memory in response to a system state of the electronic device, and receive the sensor data from the sensor circuit in response to an interrupt signal transmitted from the sensor circuit based on identifying, using the interrupt handler activation information, that the first processor processes the interrupt of the sensor circuit; wherein the instructions, when executed, cause the second processor to: receive the sensor data from the sensor circuit in response to the interrupt signal transmitted from the sensor circuit based on identifying, using the interrupt handler activation information, that the second processor processes the interrupt of the sensor circuit.

An electronic device according to various embodiments may comprise: a sensor circuit; a memory storing handler activation information; and a first processor and a second processor operatively connected to the sensor circuit and the memory. The sensor circuit may be configured to transmit an interrupt signal using an interrupt transmission unit comprising circuitry electrically connected to the first processor and the second processor, and configured to transmit sensor data using a sensor data transceiver electrically connected to the first processor and the second processor. The memory may store instructions which, when executed, cause the first processor to: amend or update interrupt handler activation information in the memory in response to a system state of the electronic device, and receive the sensor data from the sensor circuit in response to an interrupt signal transmitted from the sensor circuit based on identifying, using the interrupt handler activation information, that the first processor processes the interrupt of the sensor circuit; wherein the instructions, when executed, cause the second processor to: receive the sensor data from the sensor circuit in response to the interrupt signal transmitted from the sensor circuit based on identifying, using the interrupt handler activation information, that the second processor processes the interrupt of the sensor circuit.

Peripherals may be dynamically provisioned to containers. A peripheral arbitrator may be run in the host operating system environment to detect when containers are started. When a container is started, the peripheral arbitrator may determine which peripherals an application running in the container may use or require. The peripheral arbitrator may then identify any available peripherals matching the application's peripheral requirements and provision the peripherals to the container to thereby make the peripherals accessible to the application. In some instances, the peripheral arbitrator may use a trust score to determine whether to provision available peripherals to a container.

An interrupt request generating process can include determining a first interrupt triggering event has occurred after a predetermined period of time in which no interrupt triggering event occurred. In response to determining that the first interrupt triggering event has occurred, the interrupt request generating process may generate a first interrupt request without adding an intentional delay, and initiating a timer configured to expire after a predetermined time interval. When a second interrupt triggering event is determined to have occurred before the timer expires, a second interrupt request is delayed from being generated until the timer expires.

Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or made available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.

Provided are a computer program product, system, and method for determining when to throttle interrupts to limit interrupt processing to an interrupt processing time. Upon receiving interrupts from the hardware device, a determination is made as to whether a number of received interrupts exceeds an interrupt threshold during a interrupt tracking time period. If so, an interrupt throttling state is set to a first value indicating to only process interrupts during an interrupt processing time period. Interrupts from the hardware device are processed during the interrupt time period when the interrupt throttling state is set to the first value. Interrupts received from the hardware are masked during a processing of a scan loop of operations while the interrupt throttling has the first value and the interrupt processing time period has expired, wherein the masked interrupts are not processed while processing the scan loop of operations.

Generally, this disclosure describes systems (and methods) of moderating interrupts in a virtualization environment. An overflow interval is defined. The overflow interrupt interval is used to trigger activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

An interrupt request generating process can include determining a first interrupt triggering event has occurred after a predetermined period of time in which no interrupt triggering event occurred. In response to determining that the first interrupt triggering event has occurred, the interrupt request generating process may generate a first interrupt request without adding an intentional delay, and initiating a timer configured to expire after a predetermined time interval. When a second interrupt triggering event is determined to have occurred before the timer expires, a second interrupt request is delayed from being generated until the timer expires.

A method for generating interrupt requests, the method comprising: receiving, by a first circuit, an indication of an occurrence of an interrupt triggering event; determining whether a time difference between the occurrence of the interrupt triggering event and an occurrence of a last interrupt triggering event that preceded the occurrence of the interrupt triggering event exceeded a threshold; generating, by the first circuit, an interrupt request in response to the occurrence of the interrupt triggering event if the time difference exceeded the threshold; and delaying, for a predetermined delay period after a generation of a last interrupt request, a generating of the interrupt request that is responsive to the occurrence of the interrupt triggering event if the time difference is shorter than the threshold.

Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or make available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.