A PCI Express network card is disclosed, including a circuit board, a plate, a plurality of integrated circuits, and two heat sinks. The circuit board has five ports. The plate is provided on the circuit board and near a front edge of the circuit board, wherein the plate has a plurality of openings. The integrated circuits are provided on the circuit board, including a first processor and a second processor, which consume the most power. The first processor and the second processor are arranged in a staggered way. Each of the heat sinks abuts against the first processor and the second processor, respectively. An area of each of the heat sinks is greater than an area of each one of the first processor and the second processor. Whereby, effective heat dissipation could be achieved.

Racks and rack systems to support a plurality of sleds are disclosed herein. A rack comprises an elongated support post and a plurality of support chassis. The elongated support post extends vertically. The plurality of support chassis are coupled to the elongated support post. Each support chassis of the plurality of support chassis is sized to house a corresponding sled of the plurality of sleds.

A network input/output structure of an electronic device includes a FPGA module, a multiple of UART voltage conversion transceivers, at least one network connector and at least one detection module. Each UART voltage conversion transceiver has an input/output pin definition of a brand specification of a network device. The FPGA module uses the detection module to detect the pin definition of an external network device to confirm the brand specification of the network device and turn on a voltage conversion chip of the UART voltage conversion transceiver of the brand specification, so that the external network device can transmit network information with the electronic device automatically.

An electronic device, applied on a smart car with a plurality of sensors, includes at least one network switching circuit, at least one motherboard circuit, and a power supply circuit. The network switching circuit is coupled to the sensors of the smart car to receive sensing data from the sensors and to output the sensing data. The motherboard circuit includes a network interface controller and at least one CPU. The network interface controller is coupled to network switching circuit to receive the sensing data from the network switching circuit. The CPU is coupled to the network interface controller to perform autonomous driving for the smart car according to the sensing data. The number of network switching circuits and motherboard circuits depends on the autonomous driving level of the smart car.

A data processing system comprising: a processing subsystem supporting a plurality of consumers, each consumer being arranged to process messages received into a corresponding receive queue; a network interface device supporting a virtual interface for each of the receive queues; and a hardware accelerator coupled to the processing subsystem by the network interface device and configured to parse one or more streams of data packets received from a network so as to, for each consumer: identify in the data packets messages having one or more of a set of characteristics associated with the consumer; and frame the identified messages in a new stream of data packets addressed to a network endpoint associated with the virtual interface of the consumer so as to cause said new stream of data packets to be delivered into the receive queue of the consumer.

A system for executing a graph partitioned across a plurality of reconfigurable computing units includes a processing node that has a first computing unit reconfigurable at a first level of configuration granularity and a second computing unit reconfigurable at a second, finer, level of configuration granularity. The first computing unit is configured by a host system to execute a first dataflow segment of the graph using one or more dataflow pipelines to generate a first intermediate result and to provide the first intermediate result to the second computing unit without passing through the host system. The second computing unit is configured by the host system to execute a second dataflow segment of the graph, dependent upon the first intermediate result, to generate a second intermediate result and to send the second intermediate result to a third computing unit, without passing through the host system, to continue execution of the graph.

Systems and methods are provided for managing a data communication within a multi-level network having a plurality of switches organized as groups, with each group coupled to all other groups via global links, including: at each switch within the network, maintaining a global fault table identifying the links which lead only to faulty global paths, and when the data communication is received at a port of a switch, determine a destination for the data communication and, route the communication across the network using the global fault table to avoid selecting a port within the switch that would result in the communication arriving at a point in the network where its only path forward is across a global link that is faulty; wherein the global fault table is used for both a global minimal routing methodology and a global non-minimal routing methodology.

A network architecture including a streaming array that includes a plurality of compute sleds, wherein each compute sled includes one or more compute nodes. The network architecture including a network storage of the streaming array. The network architecture including a PCIe fabric of the streaming array configured to provide direct access to the network storage from a plurality of compute nodes of the streaming array. The PCIe fabric including one or more array-level PCIe switches, wherein each array-level PCIe switch is communicatively coupled to corresponding compute nodes of corresponding compute sleds and communicatively coupled to the network storage. The network storage is shared by the plurality of compute nodes of the streaming array.

Method for controlling commands suitable to be processed by a peripheral (2) comprising the following steps implemented by a control circuit (6) connected to a communication bus (8), a command circuit (4) and the peripheral (3) also being connected to the communication bus (8): granting or refusing authorization to the command circuit (4) to transmit a command signal of the peripheral via the bus (8), detecting the possible transmission of the command signal for the peripheral by the command circuit via the bus (8), implementing protection measures (614) when the control circuit detects that the command signal has been transmitted as the control circuit has not granted authorization, or that the command signal has not been transmitted as the control circuit has granted authorization.

A first timing error of a network device is determined based at least in part on a first received network message from a timing synchronization source. At a first instance, it is determined whether the first timing error exceeds a threshold. In response to a determination at the first instance that the first timing error exceeds the threshold, a clock of the network device is corrected based at least in part on the first received network message. A second timing error of the network device is determined based at least in part on a second received network message from the timing synchronization source. At a second instance, it is determined whether the second timing error exceeds the threshold. In response to a determination at the second instance that the second timing error does not exceed the threshold, the clock of the network device is allowed to function without correction.