An apparatus and method are described for the frame-to-frame coherency algorithm for sort-last architecture. In one embodiment of the invention, if a tile of pixels is covered completely by one triangle from a static draw call in one frame, then that tile is marked with that draw call's identifier. For the next frame, if the same static draw call is drawn, the same tile will be visited, and if the draw call's fragment passes for all pixels, it indicates that tile will contain exactly the same pixel color values as the previous frame. Hence, there is no requirement to run the pixel shader for the tile of pixels, and the color values of the tile can instead be reused from the previous frame.

A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.

A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.

A method allows changing an image raster direction from an application raster direction to a screen raster direction, in-flight while pixel values of an image are transferred successively from an application output memory to a display unit. A single buffer memory array is implemented between the application output memory and the display unit. Two writing orders for cells of the buffer memory array are used in turn, each being combined with a different reading order for the cells. The method can be hardware-implemented, and is adapted for burst-handling of the pixel values.

A method allows changing an image raster direction from an application raster direction to a screen raster direction, in-flight while pixel values of an image are transferred successively from an application output memory to a display unit. A single buffer memory array is implemented between the application output memory and the display unit. Two writing orders for cells of the buffer memory array are used in turn, each being combined with a different reading order for the cells. The method can be hardware-implemented, and is adapted for burst-handling of the pixel values.

A processing method and device for multi-screen splicing display are disclosed. The method includes: receiving instruction information for multi-screen splicing display, where the instruction information is used to instruct to splice at least two physical display screens for display; sending, according to the instruction information, display data to a video RAM of a virtual display screen formed by splicing the at least two physical display screens, where a size of the video RAM of the virtual display screen corresponds to a size of the virtual display screen; dividing the display data into at least two data blocks that correspond to sizes of the at least two physical display screens, and respectively sending the data blocks obtained by division to video RAMs of corresponding physical display screens.

A graphics display processing device including: a graphics processor that executes GPU instructions based on a primary drawing instruction and a secondary drawing instruction; an acquirer) that acquires the primary drawing instruction and the secondary drawing instruction; an estimator that calculates an estimated GPU processing time required for executing the GPU instructions; a determiner that determines, using the estimated GPU processing time, which of the primary drawing instruction and the secondary drawing instruction is to be executed first; an issuance controller that performs a control when the primary drawing instruction is to be executed first, causing the primary drawing instruction to be issued and issuance of the secondary drawing instruction to be postponed; an instruction issuer that issues each drawing instruction according to the control of the issuance controller; and a graphics driver that generates the GPU instructions by executing each drawing instruction issued.

A graphics display processing device including: a graphics processor that executes GPU instructions based on a primary drawing instruction and a secondary drawing instruction; an acquirer) that acquires the primary drawing instruction and the secondary drawing instruction; an estimator that calculates an estimated GPU processing time required for executing the GPU instructions; a determiner that determines, using the estimated GPU processing time, which of the primary drawing instruction and the secondary drawing instruction is to be executed first; an issuance controller that performs a control when the primary drawing instruction is to be executed first, causing the primary drawing instruction to be issued and issuance of the secondary drawing instruction to be postponed; an instruction issuer that issues each drawing instruction according to the control of the issuance controller; and a graphics driver that generates the GPU instructions by executing each drawing instruction issued.

A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.

A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.