A display panel control method for a display panel. The display panel includes at least one common electrode line and a plurality of data lines. The method provides a timing control signal including an active interval and a vertical blanking interval. The timing control signal is used to make the display panel either enter the active interval or enter the vertical blanking interval to execute corresponding operation procedures. When the display panel is in the active interval, the method provides corresponding data voltage to every data line according to the image data. When the display panel is in the vertical blanking interval, the method provides a blanking data voltage to every data line. The blanking data voltage is determined according to the polarity of the corresponding data voltage of the corresponding data line and a common voltage of the at least one common electrode line.

A light emitting element includes a first electrode, a second electrode, and a light emission layer interposed between the first electrode and the second electrode, where an emission efficiency of the light emission layer varies based on a voltage applied to at least one selected from the first electrode and the second electrode.

A display substrate and a display panel are provided. The display substrate includes a base substrate; the base substrate includes a display region and a peripheral region on at least one side of the display region; the peripheral region includes a first peripheral sub-region and a second peripheral sub-region, the display region includes a first display sub-region corresponding to the first peripheral sub-region and a second display sub-region corresponding to the second peripheral sub-region, and the second display sub-region is different from the first display sub-region; the second peripheral sub-region includes a first gate driving circuit, and the first gate driving circuit is configured to be connected to a plurality of gate scanning signal lines in the first display sub-region through a plurality of connecting lines in the display region, to respectively providing a gate scanning signal to a plurality of rows of pixel units in the first display sub-region.

A display panel driving system includes: a display panel having a first panel partition and a second panel partition; a first display driving circuit operatively connected to the first panel partition and configured to drive the first panel partition; a second display driving circuit operatively connected to the second panel partition and configured to drive the second panel partition; and a comparison circuit respectively connected to the first and second display driving circuits; each display driving circuit is utilized to collect brightness level statistics associated with the display panel partitions it drives; each display driving circuit is configured to determine a cathode voltage value associated with the display panel partition it drives and transmit the cathode voltage value to the comparison circuit for comparison for each of the panel partitions and determine a target value which is then utilized to adjust the cathode voltage of the whole display panel.

A display panel, a display device, and a drive method are provided. The display panel includes a plurality of sub-pixel units arranged in an array and a gate drive circuit, and the array includes N rows. The gate drive circuit includes a plurality of cascaded shift register units and N+1 output terminals arranged in sequence, each of the plurality of cascaded shift register units is configured to output a gate scan signal for driving at least two rows of sub-pixel units in the N rows of the array to work; pixel drive circuits of an (n)-th row of sub-pixel units are connected to an (n)-th output terminal of the gate drive circuit to receive the gate scan signal as a scan drive signal, and sensing circuits of the (n)-th row of sub-pixel units are connected to an (n+1)-th output terminal of the gate drive circuit.

An electroluminescence display apparatus includes a pixel array, including a plurality of pixels, a gate line connected to pixels adjacent thereto in a first direction in common, a data line connected to pixels adjacent thereto in a second direction intersecting with the first direction in common, and a first power line, a second power line, and an initialization voltage supply line connected to all of the plurality of pixels in common, and a panel driving circuit connected to the pixel array.

A pixel driving circuit and a display panel are provided. The pixel driving circuit includes a control unit to output a control signal by detecting a voltage difference between two opposite ends of a sampling resistor, and to turn on a fourth switch by the control signal. When the fourth switch is turned on, a second positive voltage received by the pixel driving circuit charges a second node to further speed up a voltage pulling up of the second node to improve a detecting speed of the pixel driving circuit.

A display device includes a display panel including a plurality of pixels, a controller configured to output image data and a gated clock signal, the image data including a plurality of pixel data for the plurality of pixels, and a data driver configured to receive the image data and the gated clock signal from the controller, and to sample the image data in response to the gated clock signal. The controller detects a repeated data pattern where same pixel data is repeated in the image data, generates a clock enable signal having an off level in a period in which the repeated data pattern is transferred, and gates an input clock signal in response to the clock enable signal to produce the gated clock signal.

A driving transistor is configured to control driving current for the light-emitting element. A first capacitive element and a second capacitive element are connected in series between a gate and a source of the driving transistor. A first switching transistor is configured to switch connection/disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element. A second switching transistor is configured to switch connection/disconnection between the gate and a drain of the driving transistor. A third switching transistor is configured to switch connection/disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch supply/non-supply of driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch connection/disconnection between an anode of the light-emitting element and a reset power line.

Provided is a method for driving a display device, including n rows of sub-pixels; the method includes: driving the first frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on a rows, from the 1.sup.st to a.sup.th rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−a) rows, from the (a+1).sup.th to n.sup.th rows, of sub-pixels in a second darkness insertion sub-period driving a second frame of image, including: performing normal display driving on the n rows of sub-pixels in a display driving period, performing darkness insertion driving on b rows, from the 1.sup.st to b.sup.th rows, of sub-pixels in a first darkness insertion sub-period, and performing darkness insertion driving on (n−b) rows, from the (b+1).sup.th to n.sup.th rows, of sub-pixels in a second darkness insertion sub-period.