An active-matrix display with passive-matrix pixel clusters includes pixel clusters each having a cluster controller and a display controller operable to provide pixel data to the cluster controllers. Each pixel cluster includes pixels disposed in an array of N rows (N>=2) and M columns (M>=1), (N+1) memory banks, and a cluster controller operable to control the pixels and memory banks. Each memory bank is operable to store pixel data for a row of pixels. The cluster controller is operable to input pixel data for a row of pixels and store the pixel data in an input memory bank of the (N+1) memory banks and output stored pixel data from one or more output memory banks of the (N+1) memory banks that are not the input memory bank to control corresponding one or more rows of pixels.

The present application provides a display panel and a display method thereof. The display method includes following steps: obtaining a real-time display frequency of a liquid crystal panel in response to a display operation of the display panel; and regulating backlight brightness of a backlight module according to the real-time display frequency, such that display brightness of the display panel is maintained within a target brightness range.

The present application provides a display panel and a display device. The display panel includes a gate driving circuit and a plurality of rows of pixel circuits. By electrically connecting a gate of a driving transistor in each of the pixel circuits to at least one oxide thin-film transistor, each of the pixel circuits has a low leakage characteristic, thereby realizing a low-frequency driving display of the pixel circuits. On this basis, a display time interval between two adjacent rows of the pixel circuits can be lengthened about half-frame time, thereby realizing an ultra-low-frequency driving display.

A pixel circuit comprises a first switch element comprising a first electrode to which an initialization voltage is applied, a gate electrode to which a initialization pulse is applied, and a second electrode connected to a second node; a second switch element comprising a first electrode connected to a third node or a fourth node, a gate electrode to which a sensing pulse is applied, and a second electrode to which a reference voltage is applied; a third switch element comprising a first electrode to which a data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node; and a fourth switch element comprising a first electrode connected to the third node, a gate electrode to which a first emission control pulse is applied, and a second electrode connected to the fourth node.

A the display panel includes a plurality of sub-pixels arranged in rows and columns; one scan line disposed in each of the rows of the plurality of sub-pixels; two data lines are disposed in each of the columns of the plurality of sub-pixels; a first multiplexer configured to select a data line at one side among the two data lines disposed in each column; and a second multiplexer configured to select a data line at another side among the two data lines disposed in each column that can be operated at a high speed using a 2D1G structure as well as at a low speed in an interlace scheme, thus securing 2H sensing time and removing flickering during switching between operations of pixels.

Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a drive module and a first initialization module. The drive module is configured to generate a drive current. The first initialization module is configured to supply a first initialization voltage to a first node. The first node is connected to the light-emitting element. A first control terminal of the first initialization module is configured to transmit the first initialization voltage to the first node in response to a first scan control signal. A display period of the display panel includes a first display stage and a second display stage. In the first display stage, a total effective-pulse duration of the first scan control signal is T1. In the second display stage, the total effective-pulse duration of the first scan control signal is T2. T1 < T2.

The present application provides a method, a device and a system for determining an actual option common voltage of a display panel. The method for determining the actual option common voltage of the display panel includes the following steps: acquiring a first common voltage and a second common voltage for fitting a curve; acquiring a first flicker corresponding to the first common voltage and a second flicker corresponding to the second common voltage; acquiring a first Vcom-Flicker curve according to the first common voltage and the first flicker, and acquiring a second Vcom-Flicker curve according to the second common voltage and the second flicker; and determining a common voltage at an intersection of the first Vcom-Flicker curve and the second Vcom-Flicker curve, in which the common voltage at the intersection is the actual option common voltage.

In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

A display device, includes: a display panel including a pixel electrically coupled to a gate line and a data line; a gate driver configured to provide a gate signal to the gate line; and a data driver configured to provide a data signal to the data line, wherein the gate driver is configured to sequentially provide a first gate signal and a second gate signal to the gate line during a first frame period, wherein the data driver is configured to provide a first data signal to the data line in response to the first gate signal, and to provide a second data signal to the data line in response to the second gate signal, and wherein the second data signal is different from the first data signal and varies dependent on the first data signal.

A flip-flop circuit is provided. A driver circuit is provided. The flip-flop circuit includes first to fifth input terminals and first to third output terminals, the first input terminal is supplied with a first trigger signal, the second input terminal is supplied with a second trigger signal, the third input terminal is supplied with a batch selection signal, the fourth input terminal is supplied with a first pulse width modulation signal, and the fifth input terminal is supplied with a second pulse width modulation signal. The first output terminal supplies a first selection signal in response to the first pulse width modulation signal in a period from supply of the first trigger signal to supply of the second trigger signal, the first output terminal supplies the first selection signal in a period during which the batch selection signal is supplied, the second output terminal supplies a second selection signal in response to the second pulse width modulation signal in the period from the supply of the first trigger signal to the supply of the second trigger signal, and the third output terminal supplies a third trigger signal.