G11C5/08

SEMICONDUCTOR DEVICE
20230402081 · 2023-12-14 ·

A semiconductor device capable of increasing readout margin in a nonvolatile resistive random access memory is provided. A clamping circuit applies fixed potential to each of a memory element and a reference resistive element. A pre-charge circuit pre-charges first and second nodes to power-source potential. A sense amplifier amplifies the potential difference between the potential of the first node and the potential of the second node generated after a discharge period based on cell current and reference current after pre-charging made by the pre-charge circuit. A third node is coupled to the first and second nodes through a capacitor. An electric-charge supply circuit is connected to the third node, and supplies electric charge to the third node in the discharge period.

Magnetic recording array and magnetic recording device
11017821 · 2021-05-25 · ·

A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.

Magnetic recording array and magnetic recording device
11017821 · 2021-05-25 · ·

A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.

Magnetoresistive stacks and methods therefor

A magnetoresistive device may include multiple magnetic tunnel junction (MTJ) stacks separated from each other by one or more dielectric material layers and electrically conductive vias extending through the one more dielectric material layers. Each MTJ stack may include multiple MTJ bits arranged one on top of another and the electrically conductive vias may be configured to electrically access each MTJ bit of the multiple MTJ stacks.

Magnetoresistive stacks and methods therefor

A magnetoresistive device may include multiple magnetic tunnel junction (MTJ) stacks separated from each other by one or more dielectric material layers and electrically conductive vias extending through the one more dielectric material layers. Each MTJ stack may include multiple MTJ bits arranged one on top of another and the electrically conductive vias may be configured to electrically access each MTJ bit of the multiple MTJ stacks.

High-voltage shifter with reduced transistor degradation
10998050 · 2021-05-04 · ·

Discussed herein are systems and methods for protecting against transistor degradation in a high-voltage (HV) shifter to transfer an input voltage to an access line, such as a global wordline. An embodiment of a memory device comprises memory cells and a HV shifter circuit that includes a signal transfer circuit, and first and second HV control circuits. The signal transfer circuit includes a P-channel transistor to transfer a high-voltage input to an access line. The first HV control circuit couples a bias voltage to the P-channel transistor for a first time period, and the second HV control circuit couples a stress-relief signal to the P-channel transistor for a second time period, after the first time period, to reduce degradation of the P-channel transistor. The transferred high voltage can be used to charge the access line to selectively read, program, or erase memory cells.

Magnetic recording array and magnetic recording device
10923169 · 2021-02-16 · ·

A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.

Magnetic memory, semiconductor device, electronic device, and method of reading magnetic memory

To provide a magnetic memory for storing multi-level information capable of reading while sufficiently securing a read margin. Provided is a magnetic memory including: first and second magnetic storage elements that are provided between a first wiring and a second wiring crossing each other, and are electrically connected in series; a third wiring electrically connected between the first and second magnetic storage elements; a first determination unit that determines a magnetization state of the first magnetic storage element on the basis of a current flowing to the first magnetic storage element through the third wiring; and a second determination unit that determines a magnetization state of the second magnetic storage element on the basis of a current flowing to the first and second magnetic storage elements through the first wiring, in which the determination state of the second determination unit is changed on the basis of the determination result of the first determination unit.

Magnetic memory, semiconductor device, electronic device, and method of reading magnetic memory

To provide a magnetic memory for storing multi-level information capable of reading while sufficiently securing a read margin. Provided is a magnetic memory including: first and second magnetic storage elements that are provided between a first wiring and a second wiring crossing each other, and are electrically connected in series; a third wiring electrically connected between the first and second magnetic storage elements; a first determination unit that determines a magnetization state of the first magnetic storage element on the basis of a current flowing to the first magnetic storage element through the third wiring; and a second determination unit that determines a magnetization state of the second magnetic storage element on the basis of a current flowing to the first and second magnetic storage elements through the first wiring, in which the determination state of the second determination unit is changed on the basis of the determination result of the first determination unit.

Magnetoresistance element and non-volatile semiconductor storage device using same magnetoresistance element
10756261 · 2020-08-25 · ·

The invention provides a magnetoresistance element with a configuration such that a stable switching action is possible with a current flowing in response to the application of a unipolar electrical pulse, and a non-volatile semiconductor storage device using the magnetoresistance element. A magnetoresistance element 1-1 includes a magnetic tunnel junction portion 13 configured by sequentially stacking a perpendicularly magnetized first magnetic body 22, an insulation layer 21, and a perpendicularly magnetized second magnetic body 200. The second magnetic body 200 has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer 21 side interface. A heat assist layer 28-1 that heats the second magnetic body 200 with a heat generated based on a current flowing through the magnetic tunnel junction portion 13 is further provided, and the magnetization direction of the second magnetic body 200 is reversed by the heating of the second magnetic body 200. A non-volatile semiconductor storage device 10-1 includes the magnetoresistance element 1-1, a switching element connected in series to the magnetoresistance element 1-1, information rewriting means that carries out a write and erase by causing a write current to flow through the magnetoresistance element 1-1, and reading means that reads information stored from the amount of current flowing through the magnetoresistance element 1-1.