A memory device including a memory array configured to store data, a sense amplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.

Methods for reading a memory are provided. In response to a first address signal, a first signal is obtained according to first data of the memory and a second signal is obtained according to second data of the memory by a decoding circuit. Binary representation of the first signal is complementary to that of the second signal. A first sensing signal is provided according to a reference signal and the first signal and a second sensing signal is provided according to the reference signal and the second signal by a sensing circuit. An output corresponding to the first sensing signal or the second sensing signal is output in response to a control signal, by an output buffer.

A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

A multiple operating-mode comparator system can be useful for high bandwidth and low power automated testing. The system can include a gain stage configured to drive a high impedance input of a comparator output stage, wherein the gain stage includes a differential switching stage coupled to an adjustable impedance circuit, and an impedance magnitude characteristic of the adjustable impedance circuit corresponds to a bandwidth characteristic of the gain stage. The comparator output stage can include a buffer circuit coupled to a low impedance comparator output node. The buffer circuit can provide a reference voltage for a switched output signal at the output node in a higher speed mode, and the buffer circuit can provide the switched output signal at the output node in a lower power mode.

Methods, systems, and devices for apparatus for differential memory cells are described. An apparatus may include a pair of memory cells comprising a first memory cell and a second memory cell, a word line coupled with the pair of memory cells and a plate line coupled with the pair of memory cells. The apparatus may further include a first digit line coupled with the first memory cell and a sense amplifier and a second digit line coupled with the second memory cell and the sense amplifier. The apparatus may include a select line configured to couple the first digit line and the second digit line with the sense amplifier.

Provided is an anti-fuse memory circuit. The anti-fuse memory circuit includes a memory array, a bit line (BL), and a word line (WL); an anti-fuse memory cell (FsBIn) electrically connected to the bit line (BL) through a first switch transistor (1Add); a second switch transistor (2Add) configured to connect the bit line (BL) to a transmission wire (100); a third switch transistor (3Add) configured to discharge the transmission wire (100); a reading module (102) including a first input end (+) connected to the transmission wire (100), a second input end (−) for receiving a reference voltage (VTRIP), and a sampling input end (C) for receiving a sampling signal (CLK); and a compensation module (101), connected to the third switch transistor (3Add) and configured to slow down a drop speed of a voltage at the transmission wire (100).

A storage circuit includes: the array of a memory cell MC including a variable-resistance element; a conversion circuit that converts the resistance value of each memory cell into the signal level of an electric signal; a reference signal generation circuit that generates a reference signal common to a plurality of columns; a correction circuit that corrects one of the signal level of the reference signal and the signal level of the electric signal for each column of the array of the memory cell; and an RW circuit that determines data stored in the memory cell belonging to a corresponding column by comparing one of the reference level and the signal level of the electric signal, corrected by the correction circuit, and the other of the reference level and the signal level of the electric signal.

A semiconductor structure and a memory are provided The semiconductor structure includes: a first active area pattern; a first gate pattern, a second gate pattern, a third gate pattern and a fourth gate pattern which are arranged at intervals in a first direction; a first connection pattern, arranged to connect the second gate pattern and the third gate pattern in parallel; a second connection pattern, arranged to connect the first gate pattern and the fourth gate pattern in parallel; at least two first contact hole patterns arranged in parallel; and at least two second contact hole patterns and at least two third contact hole patterns arranged in parallel.

The present invention includes apparatus and a method for reading one or more data states from an integrated circuitry memory cell, including the steps of connecting the memory cell to a bit line which is connected to an amplifier having an offset control which introduces an offset during the sensing portion of a read cycle to identify a data state stored in the memory cell.

A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.