A write tracking circuit includes a dummy memory cell coupled to a first dummy bit line, a second dummy bit line, and a dummy word line, a logic operation unit coupled to the dummy word line and to the first dummy bit line and configured to output a write feedback signal based on a logic operation of a signal on the dummy word line and a signal on the first dummy bit line, and a delay unit coupled to the dummy memory cell at a storage node. The write tracking circuit provides a correct feedback signal to the clock generation module to ensure normal operation of the peripheral circuit, when a data write operation to the dummy memory cell failed.

A method includes using a first tracking circuit corresponding to a first set of access ports of a memory macro to cause a signal transition of a first tracking signal based on an edge of a clock signal. Using a second tracking circuit corresponding to a second set of access ports of the memory macro, a signal transition of a second tracking signal is caused based on the edge of the clock signal. A reset signal is generated based on the signal transition of the first tracking signal and the signal transition of the second tracking signal. A read operation or a write operation on the memory macro is performed based on the edge of the clock signal and the reset signal.

A method of operating a memory device is provide. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compare with a clock cycle period to determine that the power nap period is less that the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

A semiconductor device of an embodiment includes a buffer configured to perform data transmission by turning on and off a first output transistor group and a second output transistor group; a first correction circuit configured to calibrate a resistance value of the buffer by controlling an on-off state of each of first transistors of the first output transistor group; a second correction circuit configured to calibrate the resistance value of the buffer by controlling an on-off state of each of second transistors of the second output transistor group; and a control circuit configured to cause the calibration by the first correction circuit to be performed in a non-communication duration other than a duration of data transmission from the buffer and cause the calibration by the second correction circuit to be performed in a duration other than a duration of the calibration by the first correction circuit.

A memory and a method for operating the memory are presented. The memory includes a memory cell, a sense amplifier configured to sense read data from the memory cell, a write driver configured to provide write data to the memory cell, a first circuit configured to enable the sense amplifier during a time period, and a second circuit configured to enable the write driver during at least a portion of the time period. The method includes enabling a sense amplifier to sense read data from a memory cell during a time period and enabling a write driver to provide write data to the memory cell during at least a portion of the time period. Another memory and method for operating the memory are presented. The memory and method further include an address input circuit configured to receive a write address while the sense amplifier is enabled.

The present invention discloses a static RAM for defensive differential power consumption analysis, comprising a replica bit-line circuit, a decoder, an address latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuit and n-bit output circuits; the output circuits comprises a sensitivity amplifier and a data latch circuit; the 1st PMOS tube, the 2nd PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 1st NMOS tube, the 2nd NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute the sensitivity amplifier; two NOR gates, the 8th PMOS tube, the 9th PMOS tube, the 10th PMOS tube, the 11th PMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the 10th NMOS tube constitute the data latch circuit; the present invention is characterized in that energy consumption in each working cycle is basically identical, which is provided with higher capability in defense of differential power analysis.

According to one embodiment, there is provided a semiconductor apparatus including a first chip and a second chip. The first chip is electrically connected to a terminal to which a signal from a host device is input. The second chip is electrically connected to the first chip. The second chip has a first duty adjustment circuit. The first chip has a second duty adjustment circuit. The first duty adjustment circuit performs first calibration operation in a first period. The second duty adjustment circuit performs second calibration operation in a second period. The first period and the second period have an overlapping period.

A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is configured to count a clock to generate a current time, program dummy data at predetermined memory cells among the plurality of memory cells at a power-off state, detect a charge loss of the predetermined memory cells when a power-on state occurs after the power-off state, and restore the current time based on the detected charge loss.

A magnetic memory device may include a bit line, a plurality of source lines, a plurality of normal cells coupled between the bit line and the plurality of source lines, and each including a magnetic resistance element and a switching element coupled in series to the magnetic resistance element and switched by a word line signal, a dummy cell coupled to the bit line, and a spin-hall effect material layer between the bit line and the magnetic resistance element. The magnetic resistance element may write data according to a first current that flows through the dummy cell and flows in a direction parallel to the magnetic resistance element, and a second current that flows through the magnetic resistance element.

Disclosed herein is an apparatus that includes a first circuit configured to measure a first time period from a first active edge of one of plurality of internal signals to a second active edge of one of the plurality of internal signals, and a second circuit configured to compare the first time period with a second time period to generate an alert signal.