Provided is a capacitor device, a unit synapse using the capacitor device, a synapse array using the unit synapses. The capacitor device comprises a semiconductor layer which include first and second doping regions formed to be spaced apart from each other and a body region formed between the first and second doping regions; a gate electrode provided above the body region; and a gate insulator stack to have a memory function and disposed between the gate electrode and the semiconductor layer. The capacitance between the gate electrode and the first doping region is determined according to information stored in the gate insulator stack, and the state of the capacitor device is determined according to the capacitance to be one of two preset states. The unit synapse comprises a pair of capacitor devices to perform an XNOR operation.

A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

A memory device with reduced latency is provided. The memory device includes a burst read mode with a burst length of M.sub.0 (M.sub.0 is an integer greater than or equal to 2), a global sense amplifier array, M.sub.0 local memory cell arrays <1> to <M.sub.0>, and M.sub.0 local sense amplifier arrays <1> to <M.sub.0>. A memory cell includes a transistor and a capacitor. A local memory cell array <J> (J is an integer from 1 to M.sub.0) is stacked over a local sense amplifier array <J>. The local memory cell array <J> comprises M.sub.0 blocks <J_1> to <J_M.sub.0> differentiated by row, The local sense amplifier array <J> in an idle state retains the data of the block <J_J>. The block <J_J> is specified when the local memory cell array <J> is the first local memory cell array to be accessed in a burst read mode.

A memory device with reduced latency is provided. The memory device includes a burst read mode with a burst length of M.sub.0 (M.sub.0 is an integer greater than or equal to 2), a global sense amplifier array, M.sub.0 local memory cell arrays <1> to <M.sub.0>, and M.sub.0 local sense amplifier arrays <1> to <M.sub.0>. A memory cell includes a transistor and a capacitor. A local memory cell array <J> (J is an integer from 1 to M.sub.0) is stacked over a local sense amplifier array <J>. The local memory cell array <J> comprises M.sub.0 blocks <J_1> to <J_M.sub.0> differentiated by row, The local sense amplifier array <J> in an idle state retains the data of the block <J_J>. The block <J_J> is specified when the local memory cell array <J> is the first local memory cell array to be accessed in a burst read mode.

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

A method and arrangement for performing a vector-matrix multiplication by synaptic components includes—a matrix arrangement of components in a differential arrangement, which are periodically charged and discharged; and—a clock generator, which connects the bit lines alternately to a charge integration amplifier or to a ground by means of a changeover switch. The method and arrangement addresses the problem of implementing a switched capacitor arrangement which uses capacitive, resistive or capacitive-resistive components and which uses different variations of an alternating voltage signal as an input variable. The word lines of the matrix are connected to one or more oscillators and the clock generator either reacts to rising or falling voltages of the oscillators or reacts to a positive or negative value range of the voltage of the oscillators.

In some examples, an electronic device comprising an input ferroelectric (FE) capacitor, an output FE capacitor, and a channel positioned beneath the input FE capacitor and positioned beneath the output FE capacitor. In some examples, the channel is configured to carry a magnetic signal from the input FE capacitor to the output FE capacitor to cause a voltage change at the output FE capacitor. In some examples, the electronic device further comprises a transistor-based drive circuit electrically connected to an output node of the output FE capacitor. In some examples, the transistor-based drive circuit is configured to deliver, based on the voltage change at the output FE capacitor, an output signal to an input node of a second device.

A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.