Systems and techniques that facilitate TLS-based optimization of Stark tone tuning are provided. In various embodiments, a system can comprise a receiver component that can access a qubit topology. In various aspects, the system can further comprise an optimization component that can identify, based on a set of two-level-system, (TLS) frequency regions of the qubit topology, one or more Stark tone frequencies. In various instances, the system can further comprise an execution component that can apply, to a qubit lattice corresponding to the qubit topology, one or more Stark tones that have the one or more Stark tone frequencies, thereby eliminating frequency collisions in the qubit lattice.

A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

Superconducting computing system housed in a liquid hydrogen environment and related aspects are described. An example superconducting computing system includes a housing, arranged inside a liquid hydrogen environment, where a lower pressure is maintained inside the housing than a pressure outside the housing. The superconducting computing system further includes a substrate, arranged inside the housing, having a surface, where a plurality of components attached to the surface is configured to provide at least one of a computing or a storage functionality, and the substrate further comprises a plurality of circuit traces for interconnecting at least a subset of the plurality of the components. The housing is configured such that each of the plurality of components is configured to operate at a first temperature, where the first temperature is below 4.2 Kelvin, despite the liquid hydrogen environment having a second temperature greater than 4.2 Kelvin.

One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.

One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.

An electronic device (e.g., a superconducting memory cell) includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material is patterned to form a plurality of distinct instances of the layer of superconducting material including: a first wire; and a loop that is (i) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state. The loop is configured to form a persistent current via the capacitive coupling in response to a write current applied to the first wire while the loop and the first wire are in the superconducting state. The persistent current represents a logic state of the electronic device.

An electronic device (e.g., a superconducting memory cell) includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material is patterned to form a plurality of distinct instances of the layer of superconducting material including: a first wire; and a loop that is (i) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state. The loop is configured to form a persistent current via the capacitive coupling in response to a write current applied to the first wire while the loop and the first wire are in the superconducting state. The persistent current represents a logic state of the electronic device.

Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes using a processor, processing information pertaining to a type of task to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of a shared space. The method further includes using the processor, generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a task-specific factor pertinent to the type of task. The method further includes automatically scheduling parallel execution of tasks associated with any of the plurality of inflated areas of reach satisfying a spatial constraint.

Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes using a processor, processing information pertaining to a type of task to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of a shared space. The method further includes using the processor, generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a task-specific factor pertinent to the type of task. The method further includes automatically scheduling parallel execution of tasks associated with any of the plurality of inflated areas of reach satisfying a spatial constraint.