One example includes a memory circuit. The memory circuit includes a memory array in which contiguous rows of the memory array are organized as a write-bypass portion that comprises a first portion of the rows and a main memory portion that includes a remaining portion of the rows. A given data word is stored in each of a row in the write-bypass portion and another row in the main memory portion during a data write operation in response to word-write signals and bit-write signals associated with each of the respective plurality of contiguous columns. The circuit also includes a control logic configured to store data associated with storage locations of the given data word in each of the row in the write-bypass portion and the other row in the main memory portion to facilitate access of the given data word during a data read operation.

One example includes a memory circuit. The memory circuit includes a memory array in which contiguous rows of the memory array are organized as a write-bypass portion that comprises a first portion of the rows and a main memory portion that includes a remaining portion of the rows. A given data word is stored in each of a row in the write-bypass portion and another row in the main memory portion during a data write operation in response to word-write signals and bit-write signals associated with each of the respective plurality of contiguous columns. The circuit also includes a control logic configured to store data associated with storage locations of the given data word in each of the row in the write-bypass portion and the other row in the main memory portion to facilitate access of the given data word during a data read operation.

A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

One embodiment describes a quantum memory system. The system includes an array controller that comprises a plurality of flux pumps configured to provide write currents in a write operation and read currents in a read operation with respect to a plurality of quantum memory cells, the array controller being configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.

One embodiment describes a quantum memory system. The system includes an array controller that comprises a plurality of flux pumps configured to provide write currents in a write operation and read currents in a read operation with respect to a plurality of quantum memory cells, the array controller being configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.

A reversible memory element is provided. The reversible memory element comprises a reversible memory cell comprising a Josephson junction and a passive inductor. A ballistic interconnect is connected to the reversible memory cell by a bidirectional input/output port. A polarized input fluxon propagating along the ballistic interconnect exchanges polarity with a stationary stored fluxon in the reversible memory cell in response to the input fluxon reflecting off the reversible memory cell.

A reversible memory element is provided. The reversible memory element comprises a reversible memory cell comprising a Josephson junction and a passive inductor. A ballistic interconnect is connected to the reversible memory cell by a bidirectional input/output port. A polarized input fluxon propagating along the ballistic interconnect exchanges polarity with a stationary stored fluxon in the reversible memory cell in response to the input fluxon reflecting off the reversible memory cell.

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

Method and circuit for reading a value {circumflex over (σ)}.sub.z stored in a quantum information unit (qubit) memory having a qubit frequency ω.sub.a, with a resonator defined by a resonator damping rate κ, a resonator frequency ω.sub.r, a resonator electromagnetic field characterized by â.sup.† and â, a longitudinal coupling strength g.sub.z, an output â.sub.out and a longitudinal coupling g.sub.z{circumflex over (σ)}.sub.z(â.sup.†+â). At a quantum non-demolition (QND) longitudinal modulator, periodically modulating the longitudinal coupling strength g.sub.z with a signal of amplitude {tilde over (g)}.sub.z at least three (3) times greater than the resonator damping rate κ and of frequency ω.sub.m with ω.sub.m+κ resonant with ω.sub.r, wherein the longitudinal coupling strength g.sub.z varies over time (t) in accordance with g.sub.z(t)=g.sub.z+{tilde over (g)}.sub.z cos(ω.sub.mt) with g.sub.z representing an average value of g.sub.z and at a QND homodyne detector, measuring the value {circumflex over (σ)}.sub.z of the qubit memory from a phase reading of the output {circumflex over (σ)}.sub.out.

Method and circuit for reading a value {circumflex over (σ)}.sub.z stored in a quantum information unit (qubit) memory having a qubit frequency ω.sub.a, with a resonator defined by a resonator damping rate κ, a resonator frequency ω.sub.r, a resonator electromagnetic field characterized by â.sup.† and â, a longitudinal coupling strength g.sub.z, an output â.sub.out and a longitudinal coupling g.sub.z{circumflex over (σ)}.sub.z(â.sup.†+â). At a quantum non-demolition (QND) longitudinal modulator, periodically modulating the longitudinal coupling strength g.sub.z with a signal of amplitude {tilde over (g)}.sub.z at least three (3) times greater than the resonator damping rate κ and of frequency ω.sub.m with ω.sub.m+κ resonant with ω.sub.r, wherein the longitudinal coupling strength g.sub.z varies over time (t) in accordance with g.sub.z(t)=g.sub.z+{tilde over (g)}.sub.z cos(ω.sub.mt) with g.sub.z representing an average value of g.sub.z and at a QND homodyne detector, measuring the value {circumflex over (σ)}.sub.z of the qubit memory from a phase reading of the output {circumflex over (σ)}.sub.out.