Cross-point memory cells, non-volatile memory arrays, methods of reading a memory cell, methods of programming a memory cell, and methods of writing to and reading from a memory cell are described. In one embodiment, a cross-point memory cell includes a word line extending in a first direction, a bit line extending in a second direction different from the first direction, the bit line and the word line crossing without physically contacting each other, and a capacitor formed between the word line and the bit line where such cross. The capacitor comprises a dielectric material configured to prevent DC current from flowing from the word line to the bit line and from the bit line to the word line.

A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2.sup.n. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2.sup.n+1. The plurality of second memory cells may be configured to activate in response to a second selection signal.

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a voltage distribution metric associated with a at least part of a block of the memory device; determining a threshold value for the voltage distribution metric associated with the block; and responsive to determining that the voltage distribution metric exceeds the threshold value, performing a media management operation with respect to the block.

A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.

A novel semiconductor device, a semiconductor device capable of storing multi-level data, a semiconductor device with low power consumption, a semiconductor device with a reduced area, or a highly reliable semiconductor device is provided. The semiconductor device includes a memory cell which includes a first transistor and a capacitor, and a second transistor. The first transistor includes an oxide semiconductor in a channel formation region. One of a source and a drain of the first transistor is electrically connected to a first wiring. The other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor. The other of the electrodes of the capacitor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the first wiring.

A semiconductor device with a reduced area and capable of higher integration and larger storage capacity is provided. A multi-valued memory cell including a reading transistor which includes a back gate electrode and a writing transistor is used. Data is written by turning on the writing transistor so that a potential according to the data is supplied to a node where one of a source electrode and a drain electrode of the writing transistor and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor and holding a predetermined potential in the node. Data is read by supplying a reading control potential to a control signal line connected to one of a source electrode and a drain electrode of the reading transistor, and then detecting potential change of a reading signal line.

Provided is a semiconductor device including first to sixth capacitors, first to fourth wirings, first and second sense amplifiers, and a memory cell array over the first and second sense amplifiers. The first wiring is electrically connected to the memory cell array, one electrode of the first capacitor, the third wiring via a source and a drain of a first transistor, the fourth wiring via the fifth capacitor, and the second wiring via the first sense amplifier. The second wiring is electrically connected to one electrode of the second capacitor, the fourth wiring via a source and a drain of a second transistor, and the third wiring via the sixth capacitor. The third wiring is electrically connected to one electrode of the third capacitor, and the fourth wiring via the second sense amplifier. The fourth wiring is electrically connected to one electrode of the fourth capacitor.

A computation circuit includes a computing cell array configured to provide a plurality of physical values respectively corresponding to a plurality of elements of a matrix; a vector input circuit configured to provide a plurality of input voltages corresponding to an input vector to the computing cell array; and a vector output circuit configured to output a plurality of output voltages each corresponding to a dot product between the input vector and a column vector of the matrix according to the plurality of input voltages and the plurality of effective capacitances.

A memory cell arrangement is provided that may include: one or more memory cells, each memory cell of the one or more memory cells including: a field-effect transistor structure; a plurality of first control nodes; a plurality of first capacitor structures, a second control node; and a second capacitor structure including a first electrode connected to the second control node and a second electrode connected to a gate region of the field-effect transistor. Each of the plurality of first capacitor structures includes a first electrode connected to a corresponding first control node of the plurality of first control nodes, a second electrode connected to the gate region of the field-effect transistor structure, and a spontaneous-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure.

Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.