Disclosed are a shift register unit, a gate drive circuit and a display device. The shift register unit includes: the input circuit provides the signal of the input signal end to the first node; the reset circuit provides the signal of the first reference signal end to the first node in response to the signal of the reset signal end; the control circuit controls the signals of the first node and the second node, and the output circuit provides the signal of the clock signal end to the drive output end in response to the signal of the first node, and provides the signal of the second reference signal end to the drive output end in response to the signal of the second node; the signal of the first reference signal end and the signal of the second reference signal end are loaded independently of each other.

A shift register unit, a gate drive circuit, and a drive method are provided. The shift register unit includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to charge a first node in response to a first input signal to control a level of the first node; the second input circuit is configured to charge a second node in response to a second input signal to control a level of the second node; and the output circuit is configured to output an output signal to an output terminal under common control of the level of the first node and the level of the second node.

A shift register unit, a scan driving circuit, an array substrate, a display device, and a driving method are provided. The shift register unit includes an input circuit, a replacement circuit, an output circuit, and a pull-down circuit; the input circuit is respectively connected to the input terminal and the first node, and is configured to set the first node to an active level when the input terminal (IN) is at an active level; the replacement circuit is respectively connected to the input terminal and the second node, and is configured to set the second node to an inactive level when the input terminal is at an active level.

A gate driver includes stages connected to clock signal lines to which clock signals are applied and a first gate power line to which a first gate power voltage is applied, and outputting the first gate power voltage as gate signals in response to the clock signals. The clock signals have a first frequency and the first gate power voltage has a first voltage level in a first period. The clock signals have a second frequency lower than the first frequency and the first gate power voltage has a second voltage level in a second period. One of the first and second voltage levels is a gate-on voltage level that turns on a transistor, and another of the first and second voltage levels is a gate-off voltage level that turns off the transistor.

A system and method for serializing output includes shift registers that sample a deserialized input signal at a relatively slow clock speed. Data latency between the input and output signals is controllable to a higher granularity than the input signal with bit positions corresponding to the high-speed input signal. A predictive learning algorithm receives data latency values from the input signal and corresponding data latency values from the output signal to correct and control output latency, potentially within one high speed clock cycle.

Provided is a display panel. The display panel includes multiple scanning lines, a gate driver circuit, and a timing controller. The timing controller is configured to: receive multiple data enable signals, generate a gate control signal, and provide the gate control signal for the gate driver circuit. The gate control signal includes a start signal, a first clock signal and a second clock signal. The multiple data enable signals are only within the active cycle. The timing controller is configured to generate a rising edge and a falling edge of the start signal within a time interval formed by a rising edge and a falling edge of a first data enable signal in the N.sup.th frame cycle.

Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.

Shift register includes signal writing circuit, voltage control circuit and output circuit. The signal writing circuit is configured to write inverted signal of input signal provided by signal input terminal into second node responsive to control of second clock signal provided by second clock signal terminal. The voltage control circuit is configured to write first operating voltage into first node and write second clock signal into third node in voltage control circuit in response to control of voltage at first node, write second operating voltage into third node in response to control of second clock signal and write first clock signal provided by first clock signal terminal into first node in response to control of voltage at third node and first clock signal. The output circuit is configured to write second or first operating voltage into signal output terminal in response to control of voltage at first or second node.

The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.