Examples of the present disclosure provide apparatuses and methods related to performing a sort operation in a memory. An example apparatus might include a a first group of memory cells coupled to a first sense line, a second group of memory cells coupled to a second sense line, and a controller configured to control sensing circuitry to sort a first element stored in the first group of memory cells and a second element stored in the second group of memory cells by performing an operation without transferring data via an input/output (I/O) line.

The present disclosure provides a display panel and a display device. The display panel includes a gate driving circuit including a first transistor; a base substrate; a functional layer located on a side of the base substrate, a material of the functional layer is a thermal conductive material, and the functional layer includes a first functional portion; an active layer located on a side of the functional layer away from the base substrate, the active layer includes a first active portion including at least one first active sub-portion which is configured to form a channel region of the first transistor; a second conductive layer located on a side of the active layer away from the base substrate, the second conductive layer includes a first conductive portion connected to the first functional portion through a first via hole.

An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.

A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10.sup.−18 A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

The present application discloses a shift-register unit circuit including a first input sub-circuit configured to receive a display-input signal from a display-input terminal and input a display output-control signal to a first node based on the display-input signal during a display period of one cycle of displaying one frame of image. The shift-register unit circuit also includes a second input sub-circuit configured to receive a blank-input signal for charging a blank-control node, and configured to input a blank-output-control signal to the first node based on the blank-input signal during a blank period of the one cycle. The shift-register unit circuit further includes an output sub-circuit configured to output a hybrid signal controlled by the first node. The second input sub-circuit is also configured, before an end of the blank period, to receive a first blank-reset signal to reset the blank-control node.

A display device includes a gate driving circuit and a driving circuit. The gate driving circuit outputs a clock signal. The driving circuit receives the clock signal for driving a display unit and comprises two transistors. Wherein one of the two transistors is an oxide transistor and the other one of the two transistors is a silicon transistor.

Provided are a display panel and a display device. The display panel includes a first display region, a second display region and a non-display region between the first display region and the second display region. The display panel further includes a third display region. The third display region and the non-display region at least partially overlap in the light emission direction of the display panel. In the preceding solution, the third display region is added in the display panel, and the third display region and the non-display region between the first display region and the second display region at least partially overlap in the light emission direction of the display panel, that is, the third display region covers at least part of the joint between the first display region and the second display region.

A shift register unit, a gate driving circuit, a display device and a driving method. The shift register unit includes a blank input circuit, a blank pull-up circuit, a display input circuit, and an output circuit. The blank input circuit charges and holds the level of the pull-up control node, the blank pull-up circuit uses a first clock signal to charge a pull-up node, the display input circuit charges the pull-up node, and the output circuit outputs a plurality of output clock signals respectively to a plurality of output terminals. The plurality of output terminals include a shift signal output terminal and a plurality of pixel signal output terminals. The plurality of pixel signal output terminals are configured to respectively output a plurality of pixel signals to a plurality of rows of pixel units.

A gate driving circuit is provided, which includes shift registers and a reset signal line. The shift registers respectively provide scan signals to gate lines of a display panel. Each shift register includes a precharge unit and pull-up unit. The precharge unit is coupled to a first node and outputs a precharge signal through the first node. The pull-up unit is coupled to the first node and the second node and outputs one of the scan signals to a corresponding one of the gate lines through the second node. The reset signal line is coupled to the shift registers and provides a reset signal to the shift registers. The reset signal is used to reset the shift registers after the shift registers respectively output the scan signals. The reset signal line is arranged between a layout area of the precharge unit and a layout area of the pull-up unit.