A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include multiple output stages, each of which can include a source-follower transistor coupled in series with a current sink transistor and at least one cascode transistor. The current sink transistor may have its gate terminal shorted to ground. In one arrangement, the cascode transistor has a gate terminal that receives a non-zero bias voltage. In another arrangement, the cascode transistor has a gate terminal that is also shorted to ground and operates in depletion mode.

A display panel includes sub-pixels and a scan driving circuit. The scan driving circuit includes a plurality of stages of shift registers including at least one first shift register and at least one second shift register, and a plurality of clock signal lines including at least one first sub-clock signal line and at least one second sub-clock signal line. Each shift register includes a first sub-circuit and a second sub-circuit. A first sub-clock signal line in the at least one first sub-clock signal line is electrically connected to a first sub-circuit in a first shift register in the at least one first shift register. A second sub-clock signal line in the at least one second sub-clock signal line is electrically connected to one sub-circuit of a first sub-circuit and a second sub-circuit in a second shift register in the at least one second shift register.

A display panel, a display drive circuit and a display drive method are provided in the present disclosure. The display drive circuit includes first shift registers from a first shift register of a 1st-stage to a first shift register of an Nth-stage; first shift registers of first A stages are virtual shift registers which are at least configured to make that an inputted second signal of a same pixel circuit has a delay of a set time length t relative to the first signal; and first shift registers of last (N-A) stages are at least configured to provide pixel circuits with the second signal; where t=a+b+c+d; and $A=\frac{t}{t_0*X}.$
A particular drive time sequence is formed in the present disclosure, which improves the characteristics of the drive transistor, solve the display problem caused by the tailing problem of the output signal of the first shift register, and improve image display quality.

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wiring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

A display device with a variant-shape display region other than the rectangular display region is configured to form a scanning line drive circuit, along the variant-shape display region. The scanning line drive circuit includes bus wiring group with clock wiring for supplying clocks with three or more phases and the power supply wring for supplying power, and the unit circuits for configuring the shift register including five or more transistors. The bus wiring and the unit circuits are formed on the different regions so as not to cross with one another.

A shift register circuit that controls back gate voltage of a transistor with a simple configuration and at a low cost, and a display panel. In the shift register circuit, shift registers include: an output circuit, a charge and discharge circuit, a first power supply terminal, and at least one back gate voltage generation circuit. The output circuit or the charge and discharge circuit includes at least one transistor. The back gate voltage generation circuit includes a back gate node. The back gate node is connected to the back gate electrode of the transistor. The back gate voltage generation circuit changes a voltage of the back gate node according to a voltage of a gate electrode of the transistor. The back gate voltage generation circuit is supplied with a drive voltage from the first power supply terminal.

The embodiments of the present application disclose a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit comprises an input sub-circuit connected to an input signal terminal and a pull-up control node, and configured to charge the pull-up control node under control of an input signal; and an output sub-circuit connected to the pull-up control node, a clock signal terminal, a first voltage terminal, and an output signal terminal, and configured to output a first constant voltage to the output signal terminal under control of a clock signal and the pull-up control node.

The disclosure relates to a shift register unit, a driving method of shift register units, a gate driving circuit and a display panel. The shift register unit includes: an input module, a pull-up module, a storage capacitor, an output module configured to transmit a first voltage signal to a signal output terminal under the control of the first voltage signal; and an output control module configured to transmit the first voltage signal or a second power signal to the signal output terminal under the control of the voltage signal of the pull-up node and a first selection signal, and to transmit the first voltage signal or the second power signal to the signal output terminal under the control of the voltage signal of the pull-up node and a second selection signal.

A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

The present disclosure provides a gate driving circuit, a driving method, and a display device. The gate driving circuit includes cascaded multistage gate driving units and a reset adjustment unit. Each stage of the gate driving units includes a pull-up module, a first output module, a second output module, and a reset module. The reset adjustment unit is used for, under the control of a first and a second control signal, inputting the reset signal of the reset terminal of a former stage gate driving unit to the reset module of a latter stage gate driving unit, and inputting the reset signal of the reset terminal of the latter stage gate driving unit to the reset module of the former stage gate driving unit.