A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

A shift register unit including an input circuit configured to receive a first clock signal and an input signal to provide the input signal to a first node, a first control circuit electrically connected to the first node and a second node and configured to receive the first clock signal to control a voltage of the second node, an output circuit electrically connected to the first node and an output terminal and configured to receive a second clock signal to provide an output signal to the output terminal based on the second clock signal, an output voltage control circuit electrically connected to the second node and the output terminal and configured to control a voltage of the output signal, and a discharge circuit electrically connected to the first node and the second node and configured to receive the second clock signal to achieve electrical discharge of the first node.

Embodiments of the present application disclose a shift register, and a gate drive circuit and a driving method therefor. A first control module is configured to control, based on a signal of a first clock signal terminal, a signal of a second clock signal terminal, and a level of a second node, an initial signal and a first level signal to be transmitted to a first node. A second control module controls, based on the initial signal and a signal of a third clock signal terminal, a second level signal and the signal of the third clock signal terminal to be transmitted to the second node. An output module controls, based on a level of the first node, the signal of the second clock signal terminal to be transmitted to an output terminal of the shift register.

Display panel and display device are provided. The display panel includes a driving circuit includes N-level shift registers connected in cascade with N2. A shift register of the N-level shift registers includes a first control part and a second control part. The first control part is electrically connected to the second control part. The first control part is configured to control a first output signal, and the first output signal of an i-th level shift register serves as an input signal of a j-th level shift register, where 1iN, and 1jN. The second control part includes a control unit and a first voltage stabilizing unit.

Provided are a display panel and a display device. The display region of the display panel includes multiple shift register circuit groups. The shift register circuit group includes multiple shift register units disposed sequentially in a first direction. The multiple shift register circuit groups are arranged in a second direction. The first direction and the second direction intersect. The shift register circuit group is configured to output a first scan signal and includes at least a first shift register circuit group and a second shift register circuit group, which are respectively connected to first scan signals of different rows. The display region further includes multiple signal lines extending in the first direction. The signal line includes multiple signal line groups. The signal line group is electrically connected to a respective shift register circuit group, and different signal line groups are electrically connected to different shift register circuit groups.

A gate electrode driving circuit is provided and includes: a plurality of output terminals provided in correspondence with pixel driving circuit rows, and configured to provide a pulse width modulation signal to a control terminal of a first switching unit; the gate electrode driving circuit provides the pulse width modulation signal to a pixel driving circuit subgroup in a same pixel driving circuit group in a same frame, where each pixel driving circuit group includes a plurality of pixel driving circuit rows with each including a plurality of pixel driving circuits distributed along a first direction; a part of the pixel driving circuit rows in the pixel driving circuit group form the pixel driving circuit subgroup; the gate electrode driving circuit further provides the pulse width modulation signal to different pixel driving circuit subgroups of the same pixel driving circuit group in at least a part of different frames.

The present invention provides a liquid crystal display that can reduce occurrence of quality problems and improve adhesive strength between substrates. The present invention is a liquid crystal display including a first substrate, a second substrate, and a seal. The first substrate includes a shift register monolithically formed on an insulating substrate, a plurality of bus lines, a first end, and a display region. The shift register includes a plurality of multistage-connected unit circuits and wiring connected to the plurality of unit circuits, and is arranged in a region between the first end and the display region. At least one of the unit circuits includes a clock terminal, an output terminal, an output transistor, a second transistor, and a bootstrap capacitor. The output transistor and the bootstrap capacitor are arranged in a region between the first end and one of the wiring and the second transistor.

Provided is a display panel. In the same shift register unit, an input module receives an input signal and a scan control signal and controls a signal of a first node; a reset module receives a reset clock signal and the scan control signal and controls a signal of a second node; an output module receives the signal of the first node, the signal of the second node, a first level signal, and an output clock signal and outputs a gate drive signal; and the refresh control module controls, according to the first refresh control signal, the time interval of the active level of the gate drive signal output by the shift register unit, and controls, according to the second refresh control signal, the time period of the inactive level of the gate drive signal output by the shift register unit.

A scan line to which a selection signal or a non-selection signal is input from its end, and a transistor in which a clock signal is input to a gate, the non-selection signal is input to a source, and a drain is connected to the scan line are provided. A signal input to the end of the scan line is switched from the selection signal to the non-selection signal at the same or substantially the same time as the transistor is turned on. The non-selection signal is input not only from one end but also from both ends of the scan line. This makes it possible to inhibit the potentials of portions in the scan line from being changed at different times.

A display substrate, includes: a display region. The display region includes a plurality of sub-pixels disposed on a base substrate, a plurality of first signal lines extending in a first direction, and a plurality of data lines extending in a second direction. At least one sub-pixel includes a driving circuit, and the driving circuit includes a plurality of transistors and at least one storage capacitor. The transistor at least includes a first conductive layer and a second conductive layer. The plurality of first signal lines is located in a third conductive layer. The third conductive layer is located on a side of a control electrode of a transistor of the driving circuit away from the base substrate.