A control device and a memory system are provided. The control device includes a first peripheral circuit group and a second peripheral circuit group. The first peripheral circuit group and a memory array are driven by a first voltage in a standby mode. The first peripheral circuit group provides a control command when recognizing that a command string is a deep power-down (DPD) execution command string. When receiving the control command, the second peripheral circuit group provides a DPD signal having a first logic value to stop providing the first voltage so that the memory system enters a DPD mode. In the DPD mode, when recognizing that the command string is a DPD exit command string, the second peripheral circuit group provides a DPD signal having a second logic value to provide the first voltage so that the memory system enters standby mode.

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a memory cell configured to operate in multiple retention states including a static retention state and a dynamic retention state. The integrated circuit may include a controller configured to selectively apply different voltage levels to the memory cell based on the retention state of the memory cell.

A recording and/or reproducing apparatus includes a microphone, a semiconductor memory, an operating section and a controller. An output signal from the microphone is written in the semiconductor memory and the written signals are read out from the semiconductor memory. The operating section performs input processing for writing a digital signal outputted by an analog/digital converter, reading out the digital signal stored in the semiconductor memory and for erasing the digital signal stored in the semiconductor memory. The control section controls the writing of the microphone output signal in the semiconductor memory based on an input from the operating section and the readout of the digital signal stored in the semiconductor memory. The control section operates so that, if, when the signals written in the storage section is read out from it, an input for erasure is entered by the operating section, the signal being read out from the storage section is erased when, after reading out the signal from the storage section for a pre-set period, an input for erasure is again entered from the operating section.

For solid state drive (SSD) or other memory system formed of multiple memory dies, techniques are presented for operation in a standby mode with increased power savings. The memory dies are operable in a regular standby mode and in a low power standby mode. Based upon the amount of current each of the memory dies in the regular standby mode, when the device goes into standby the memory dies that draw higher amounts of current when in the regular standby mode are instead placed into the low power standby mode. The amount of current drawn by each of the memory die in the regular standby mode can be determined for each of the memory dies at die sort or as part of the memory test process, or can be determine by an assembled SSD itself.

Devices and methods include a command input configured to receive a command for a memory device. Second stage wakeup circuitry configured to receive a portion of the command and output an indication of whether the command is a non-burst command based on the portion. Clock gating circuitry is configured to receive an input clock and a wake signal. The clock gating circuitry is also configured to output an internal clock based at least in part on a pulse of the received wake signal. The clock gating circuitry also is configured to maintain the output of the internal clock for a duration based on the indication with the duration being shorter when the indication indicates that the command is a non-burst command.

Disclosed are devices and methods for improved automotive electronic control unit reliability and safety during power standby mode. In one embodiment, a method is disclosed comprising recording statistics of a dynamic random-access memory in a device, while the device is in a power on state; detecting a command to enter a standby state; analyzing the statistics to determine whether a health check should be performed; powering down the device when determining that a health check should be performed; and placing the device in standby mode when determining that a health check should not be performed.

In accordance with an embodiment, a memory cell device includes at least one memory cell; a first switch connected between the at least one memory cell and a reference potential node; a second switch connected between the at least one memory cell and the reference potential node, and switch driver logic adapted to put the first switch selectively into one of at least three operating states by activation or deactivation of a first subcircuit of the switch driver logic, wherein the at least three operating states comprises an on state, an off state, and a conductive state in which an electrical conductivity of the first switch is lower than in the on state and higher than in the off state, and put the second switch selectively into one of the at least three operating states by activation or deactivation of a second subcircuit of the switch driver logic.

A flash memory capable of automatically releasing a deep power-down mode is provided. The flash memory includes: a standard command interface (I/F) circuit and a deep power-down mode (DPD) controller, operating through an external power voltage; and an internal circuit, operating through internal voltages supplied from voltage supply nodes. The DPD controller detects whether the flash memory is in the deep power-down mode when a standard command is inputted to the standard command I/F circuit and recovers the internal circuit from the DPD mode in the case where the deep power-down mode is detected. The standard command is executed after the internal circuit is recovered.

A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

A delay tracking method and a memory system are provided. The delay tracking method is applied to a memory system supporting a low-frequency-mode (LFM) and a high-frequency-mode (HFM) of an operating clock. The delay tracking method includes the steps of selecting a LFM oscillator for obtaining a LFM delay value when the operating clock is in the HFM; and selecting a HFM oscillator for obtaining a HFM delay value when the operating clock is in the LFM.