A non-volatile semiconductor memory is disclosed comprising a first memory device and control circuitry operable to issue an access command to the first memory device. A command status is requested from the first memory device after a status delay. When the command status indicates the first memory device has completed the command, a first access time of the memory device is measured. An access sequence of the first memory device is then modified in response to the access time.

In an example, a serial peripheral interface (SPI) flash memory controller includes a transmit first-in-first-out (FIFO) circuit and an SPI interface operable to provide an interface between the transmit FIFO and an SPI flash memory. The SPI flash memory controller further includes a random access memory (RAM) operable to store a memory interface file, an address interface of the RAM operable to receive a command from the transmit FIFO circuit, a data interface of the RAM operable to output a control word associated with the command. The SPI flash memory controller further includes state machine logic operable to set behavior of the SPI interface based on the control word output from the RAM, where the control word includes a data direction field, a data phase field, an addressing width field, an addressing phase field, and a command error field.

A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Various embodiments are disclosed for automatic transmission of dummy bits in a serial bus master. The disclosed embodiments allow a single DMA descriptor to be fetched from memory for the reception of a specified amount of data. Dummy bits can be located or generated in the serial bus master either as a user configurable value or a default value. Logic in the serial bus master initiates a data transfer by writing a count value representing an amount of data to be received to a count register in the serial bus master. The single DMA descriptor is then configured to handle the internal transfer of bits received by the serial bus master from a serial bus slave and the DMA controller is enabled. When data transfer is initiated, the serial bus master starts sending dummy bits to the serial bus slave and receiving data bits from the serial bus slave.

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

A programmable integrated circuit (IC) comprising a single body of semiconductor is disclosed. The IC comprises at least one optical transducer as an integral part of the programmable integrated circuit on the same body of semiconductor, the optical transducer being operable to receive an optical input indicative of programming instructions and at least one storage element communicatively coupled to the optical transducer and being operable to store thereon the programming instructions or an adaptation thereof. The programming instructions received via the optical input are configured to direct the operation of the IC.

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

A programmable integrated circuit (IC) comprising a single body of semiconductor is disclosed. The IC comprises at least one optical transducer as an integral part of the programmable integrated circuit on the same body of semiconductor, the optical transducer being operable to receive an optical input indicative of programming instructions and at least one storage element communicatively coupled to the optical transducer and being operable to store thereon the programming instructions or an adaptation thereof. The programming instructions received via the optical input are configured to direct the operation of the IC.

A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.