In accordance with aspects of the present invention, a method of synchronizing two integrated circuits is presented. A method of synchronizing two integrated circuits can include sending a first pulse from a master IC to a slave IC over a SYNC bus; receiving a second pulse on the SYNC bus from the slave IC; checking the second pulse; triggering an interrupt if a failure is detected; and initiating measurement if synchronization is detected.

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V.sub.glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V.sub.trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V.sub.bias, wherein V.sub.bias is chosen such that either both conditions (V.sub.bias<V.sub.trip) and (V.sub.bias+V.sub.glitch>V.sub.trip) or both conditions (V.sub.bias>V.sub.trip) and (V.sub.biasV.sub.glitch<V.sub.trip) are always true.

Various illustrative embodiments pertain to a signal quality evaluation system having a decision feedback equalizer (DFE) and a signal quality evaluator. The DFE receives an input signal containing symbols that represent digital data and uses the symbols to generate multiple detection thresholds. Each detection threshold is one of several detection thresholds that can be generated by the DFE by processing one or more symbols present in the input signal prior to a current clock cycle of a clock that is recovered from the input signal. The signal quality evaluator uses the detection thresholds provided by the DFE to detect transitions in the input signal. The signal quality evaluator may execute jitter measurements and/or time interval error (TIE) measurements by evaluating the transitions in the input signal.

Radio-frequency (RF) signal analysis includes slow-time signal processing and fast-time signal processing. Incoming RF pulses are captured according to a resource scheduling configuration. The fast-time signal processing is to prioritize the captured RF pulses for slow-time signal processing based on dynamic pulse-grading criteria. The slow-time signal processing is to perform relevance evaluation of the prioritized RF pulses, and to adjust the dynamic pulse-grading criteria and the resource scheduling configuration based on the relevance evaluation.

A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

A circuit for measuring a transition time of a digital signal may be provided. The circuit comprises a window detector comprising a comparator circuitry arranged for generating a first signal based on comparing said digital signal with a first reference voltage and for generating a second signal based on comparing said digital signal with a second reference voltage. Additionally, the circuit comprises a time-difference-to-digital converter operable for converting a delay between an edge of said first signal and an edge of said second signal into a digital value, said digital value characterizing said transition time of said digital signal.

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V.sub.glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V.sub.trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V.sub.bias, wherein V.sub.bias is chosen such that either both conditions (V.sub.bias<V.sub.trip) and (V.sub.bias+V.sub.glitch>V.sub.trip) or both conditions (V.sub.bias>V.sub.trip) and (V.sub.biasV.sub.glitch<V.sub.trip) are always true.

An occurrence of a first set of n periods of a frequency-shift-keying (FSK)-modulated waveform is counted, where n is an integer number. The n periods of the FSK-modulated waveform in the first set have a first time duration. An occurrence of a second set of n periods of the waveform is counted. The n periods of the waveform in the second set have a second time duration. The first time duration is determined based on the counting of the first set of n periods. The second time duration is determined based on the counting of the second set of n periods. A difference between the first time duration and the second time duration is compared to a threshold. Changes in frequency of the waveform are detected based on the comparing of the difference between the first time duration and the second time duration to the threshold.

An integrated circuit with clock detection and selection function for use in a storage device includes: an embedded oscillator, a detection circuit and a selection circuit. The embedded oscillator is configured to generate an embedded clock signal. The detection circuit includes a sampling and counting circuit and a clock determination circuit. The detection circuit, and is configured to detect existence of a reference clock signal provided by a host based on sampling and counting operations that are performed according to a signal on a clock signal lane and the embedded clock signal. The selection circuit is coupled to the detection circuit and the embedded oscillator, and is configured to select one of the embedded clock signal and the signal on the clock signal lane according to the existence of the reference clock signal as an output clock signal, thereby to provide the output clock signal to the storage device.

An FPGA clock signal self-detection method relates to the technical field of control module, and the technical problem to be solved is to improve operational reliability and safety of the FPGA chip. The method comprises introducing two clock signals to an FPGA chip, wherein one clock signal is a first clock signal, and the other clock signal is a second clock signal; using the first clock signal to control all synchronous logic operations in the FPGA chip, and using the second clock signal to detect the first clock signal for correctness. The method of the invention is particularly applicable to a system with the FPGA chip as a main controller or important control unit.