A method for sensing the current in a high-electron-mobility transistor (HEMT) that compensates for changes in a drain-to-source resistance of the HEMT. The method includes receiving a sense voltage representative of the current in the HEMT, receiving a compensation signal representative of a drain-to-source voltage of the HEMT, and outputting as a compensated sense voltage a linear combination of the sense voltage and the compensation signal.

An online monitoring system for measuring the on-state voltage drop of power semiconductor devices comprises a voltage withstanding circuit and a voltage clamping circuit, one terminal of the voltage withstanding circuit is connected to one terminal of the voltage clamping circuit, and the other terminals of the voltage withstanding circuit and the voltage clamping circuit are randomly connected to two terminals of the power semiconductor device under test (DUT) respectively. The two terminals of the voltage clamping circuit are output terminals of the online monitoring system. A clamping voltage of the voltage clamping circuit is higher than the on-state voltage drop of the DUT. When the DUT is off, the output voltage of the system is fixed to the clamping voltage, and when it is on, the output voltage is not clamped. The system has simplified structure and enables convenient, accurate and low-cost measurement of on-state voltage drop.

The present application discloses a method and apparatus for calculating the kink current of SOI device, which is used to solve the problem that the kink current calculation in the prior art is not accurate and is not suitable for circuit simulation. The method includes: obtaining the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current of the SOI device respectively; and calculating the kink current of the SOI device according to the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current.

The invention discloses a fabrication process variation analysis method of a silicon-based Mach-Zehnder electro-optic modulator. The method includes the following steps: (1) use the input reflection coefficient S.sub.11 to characterize and quantify the reflection deviation characteristics of the driving signal on the traveling wave electrode; (2) measure and quantify the modulated signal characteristics of the silicon Mach-Zehnder electro-optic modulator. The modulated signal characteristics include transmission characteristics, vertical direction characteristics and horizontal direction characteristics; (3) Pearson correlation coefficient and partial correlation coefficient are introduced. By analyzing the value and variation trend of Pearson correlation coefficient and partial correlation coefficient, the relationship between the deviation of the driving signal reflection and the deviation of the modulated signal characteristics is analyzed. The method of the present invention can establish the relationship between fabrication process control and performance analysis at the device level, and help to develop device designs with better fabrication tolerances.

A diagnostic device includes: a generation circuit that generates an inspection signal that is an alternating current signal of a single frequency, a conversion circuit that converts, into a direct current signal, a response signal of a piezoelectric element in response to the inspection signal, and a controller that analyzes the direct current signal and determines whether the piezoelectric element operates normally based on the analysis of the direct current signal.

The subject application provides an apparatus and method for measuring dynamic on-resistance of a device under test (DUT) comprising a control terminal electrically connected to an output of a first controlling module being configured to generate a first control signal to switch on and off the DUT. The apparatus comprises a switching device and a second controlling module configured to: receive the first control signal from the first controlling module and generate a second control signal to switch on and off the switching device such that the switching device is turned on later than the DUT for a first time interval and turned off earlier than the DUT for a second time interval.

A method and system for monitoring a change in leakage current through a transient voltage suppressor, TVS, device, the method comprising locating a tunnel magneto-resistance, TMR, device in proximity to the TVS device and measuring the change in resistance of the TMR device.

A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

The present application discloses a method and apparatus for calculating the kink current of SOI device, which is used to solve the problem that the kink current calculation in the prior art is not accurate and is not suitable for circuit simulation. The method includes: obtaining the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current of the SOI device respectively; and calculating the kink current of the SOI device according to the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current.

A wafer includes a process control monitor (PCM) structure formed on a substrate. The PCM structure includes detection and reference structures. The detection structure includes a first electrically conductive line arrangement formed in a first structural layer on the substrate and a first protection layer surrounding the first electrically conductive line arrangement. The reference structure includes a second electrically conductive line arrangement formed in the first structural layer on the substrate, a second protection layer surrounding the second electrically conductive line arrangement, an insulator material formed overlying the second electrically conductive line arrangement and the second protection layer, and a second structural layer overlying the insulator material. The insulator material does not overlie the detection structure. Methodology entails measuring a capacitance between the detection structure and the substrate, measuring another capacitance between the reference structure and substrate, and comparing the two capacitances to determine whether defects exist.