Implementations of methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.

A method for controlling temperature in a temperature control system. The method includes providing a temperature control system including a controller, a first contactor assembly having a first channel system, a plurality of first contacts, each of the first contacts including a portion that is disposed within the first channel system, and one or more of a first exhaust valve or a first inlet valve, and a second contactor assembly having a second channel system, a plurality of second contacts, each of the second contacts including a portion that is disposed within the second channel system, and one or more of a second exhaust valve or a second inlet valve. The method also includes receiving, by the first contactor assembly, a fluid at a first temperature. The method also includes receiving, by the second contactor assembly, the fluid at the first temperature.

An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. There are test circuit sites in the scribe lines, each test circuit site including contact pads for simultaneous connection to probe card needles, sensor circuit select and control circuitry, and a sensor circuit bank.

An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Selection circuitry is positioned within the scribe lines. The selection circuitry is connected to test circuits in the scribe lines. The selection circuitry operates to enable voltage control at a single test circuit while disabling all other test circuits.

A probing apparatus includes a frame, a testing device, a rotatable testing platform, and a probe module. The testing device is disposed on the frame and is displaceable along an X direction and a Y direction perpendicular to the X direction. The rotatable testing platform is disposed on the frame and is rotatable around a rotating axis extending in the X direction. A direction perpendicular to the X direction and the Y direction is a Z direction, and the rotatable testing platform and the testing device are located at different positions of the Z direction. The probe module is disposed on the rotatable testing platform.

There is provided an insertion/extraction mechanism for having one or multiple block members being inserted into or extracted from a frame member forming an intermediate connection member that is disposed between a first member having multiple first members and a second member having multiple second terminals and electrically connects the first terminals and the second terminals, the block member having multiple connection terminals for electrically connecting the first terminals and the second terminals. The insertion/extraction mechanism comprises a first engaging unit and a second engaging unit that are engaged with a first engaged portion and a second engaged portion of the block member, respectively, thereby holding the block member.

In an imaging method, a focal point of a focused optical beam is sequentially mechanically positioned at coarse locations in or on an integrated circuit (IC) wafer or chip. At each coarse location, a two-dimensional (2D) image or mapping tile is acquired by steering the focal point to fine locations on or in the IC wafer or chip using electronic beam steering and, with the focal point positioned at each fine location, acquiring an output signal produced in response to an electrical charge that is optically injected into the IC wafer or chip at the fine location by the focused optical beam. The 2D image or mapping tiles are combined, including stitching together overlapping 2D image or mapping tiles, to generate an image or mapping of the IC wafer or chip. The electronic beam steering may be performed using a galvo mirror. The set of coarse locations may span a three-dimensional (3D) volume.

A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.

According to one embodiment, a processing information management system includes: an abnormality analyzer configured to generate abnormality occurrence data of a target wafer based on processing location information, the processing location information collected based on a first sensor outputting a first sensor signal according to a detected processing state, the first sensor provided in a wafer processing apparatus; and an integration system configured to integrate the abnormality occurrence data into wafer map data corresponding to the target wafer.

Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG. The physical contacting to the topside of the wafer is noncontaminating and noninvasive to the semiconductor layers.