Proposed is a wafer inspection apparatus and a wafer inspection method, which can increase inspection accuracy while reducing the amount of dry air used. The wafer inspection apparatus includes a chamber providing a space for an electrical test of a wafer, a support unit positioned inside the chamber to support the wafer, a temperature control unit for controlling a test temperature of the wafer, a dry air supply unit for supplying dry air to the chamber, and a flow control unit for controlling the dry air supply unit to adjust flow rate of the dry air based on the test temperature. The wafer inspection apparatus and the wafer inspection method of the present disclosure may increase the accuracy of the wafer inspection while preventing the drying air from being wasted by variably adjusting the flow rate of dry air supplied based on the test temperature of the wafer.

The present application discloses a testing device of array substrates and a testing method. The testing device of array substrates includes: a machine and testing interfaces, the testing interfaces being disposed on the machine; and testers disposed above the machine. There are at least two sets of testers, and the testers synchronously operate according to a preset scheme.

There is provided an alignment method of a probe card including a plurality of probe groups provided corresponding to a plurality of chips, comprising: a first mode for calculating a gradient and a center of a probe group based on position information of two or more probes included in the probe group for each of the plurality of chips and calculating a gradient and a center of the probe card based on the calculated grandients and the calculated centers of the plurality of probe groups.

To measure the resistance area product of a high resistivity layer using a microscopic multi point probe, the high resistivity layer is sandwiched between two conducting layers. A plurality of electrode configurations/positions is used to perform three voltage or resistance measurements. An equivalent electric circuit model/three layer model is used to determine the resistance area product as a function of the three measurements.

A balanced on-wafer load pull tuner system includes an intelligent, independent and universal mechanical balancing and contact controlling device, supporting automatic microwave single or multi-probe slide screw tuners. It allows contacting and stable on-wafer testing of sub-micrometric devices. Ultra-low loss rigid airlines (bend-lines) used to connect the tuner with the semiconductor chips, in order to improve the tuning range at the DUT reference plane, transfer mechanical movements of the wafer probes attached to the rigid bend-lines, when the tuner mobile carriages move horizontally. A precisely controlled counter-weight allows contacting the DUT and balanced load pull operation by controlling the center of gravity of the assembly.

A method of testing an integrated circuit die (IC) for cracks includes performing an assembly process on a wafer including multiple ICs including: lowering a tip of a first manipulator arm to contact and pick up a given IC, flipping the given IC such that a surface of the IC facing the wafer faces a different direction, and transferring the IC to a tip of a second manipulator arm, applying pressure from the second manipulator arm to the given IC such that pogo pins extending from the tip of the first manipulator arm make electrical contact with conductive areas of the IC for connection to a crack detector on the IC, and performing a conductivity test on the crack detector using the pogo pins. If the conductivity test indicates a lack of presence of a crack, then the second manipulator arm is used to continue processing of the given IC.

The invention discloses a wafer testing device of flip chip VCSEL for testing a wafer having a plurality of light emitting units. The wafer testing device of flip chip VCSEL comprises a wafer testing carrier and a flexible conductive layer. The wafer testing carrier has a first surface. A plurality of testing portions are disposed on the first surface. The flexible conductive layer, detachably disposed on the first surface, are conductive in vertical direction and insulated in horizontal direction. Wherein the wafer is disposed on the flexible conductive layer, and each light emitting unit is electrically connected with one of the testing portions in vertical direction through the flexible conductive layer while testing the wafer.

A probe card includes a sub-board, having a heating layer, connected to a probe pin. A main board is connected to the sub-board and includes a first output terminal configured to output first power received from a first power supply to the heating layer in a first mode. A power converter is configured to lower a first voltage corresponding to residual power received from the first power supply to a second voltage and output the residual power in a second mode. A second output terminal is configured to receive the residual power from the power converter and second power from a second power supply and output third power including the residual power and the second power to a device under test in the second mode. A first switch unit is connected to the first power supply, the first output terminal, and the power converter.

An inspection system includes a plurality of inspection apparatuses, and a data processing apparatus capable of communicating with the plurality of inspection apparatuses. The data processing apparatus includes a storage part storing a model that determines a causal relationship between an apparatus parameter related to setting of the plurality of inspection apparatuses and index data obtained when the plurality of inspection apparatuses are operated, a collection part collecting the apparatus parameter and the index data, a determination part determining whether or not the index data is included in a predetermined allowable range, and a calculation part calculating an adjustment amount for adjusting the apparatus parameter, based on the apparatus parameter and the index data, and the model, when it is determined that the index data is not included in the predetermined allowable range.

A stage on which an inspection object having an electronic device against which a contact terminal of a probe card of an inspection apparatus is pressed by a load applied thereto is placed, includes a first cooling plate including a first coolant flow path formed therein, a heating source mounted on the first cooling plate and including a plurality of light emitting elements so as to heat the inspection object, a transparent member provided on the heating source and transmitting light output from the heating source, a second cooling plate provided on the transparent member so as to hold the inspection object and including a second coolant flow path formed therein, and a transparent resin layer filled between the first cooling plate and the transparent member so as to cover the heating source.