An inspection jig includes: film-shaped wiring substrates each having one surface provided with an electrode; a pedestal that supports the wiring substrates which are laminated such that electrode regions are exposed, the electrode region being a region where the electrode is provided in each of the wiring substrates; and a plurality of probes which have base end portions in contact with the electrode regions and extend in a direction away from the electrode regions.

A semiconductor device may include: first to n-th through-electrodes; first to n-th through-electrode driving circuits suitable for charging the first to n-th through-electrodes to a first voltage level, or discharging the first to n-th through-electrodes to a second voltage level; and first to n-th error detection circuits, each suitable for storing the first voltage level or the second voltage level of a corresponding through-electrode of the first to n-th through-electrodes as a down-detection signal and an up-detection signal, and outputting a corresponding error detection signal of first to n-th error detection signals by sequentially masking the down-detection signal and the up-detection signal.

A semiconductor device includes a semiconductor substrate having a main surface over which a plurality of die pads and at least one alignment pad for optical process control for semiconductor wafer probing are arranged. The alignment pad has a hardness smaller than a hardness of the plurality of die pads.

A system and method for Z-PAT defect-guided statistical outlier detection of semiconductor reliability failures includes receiving electrical test bin data with semiconductor die data for a plurality of wafers in a lot generated by a statistical outlier detection subsystem configured to perform Z-direction Part Average Testing (Z-PAT) on test data generated by an electrical test subsystem after fabrication of the plurality of wafers in the lot, receiving characterization data for the plurality of wafers in the lot generated by a semiconductor fab characterization subsystem during the fabrication of the plurality of wafers in the lot, determining a statistical correlation between the electrical test bin data and the characterization data at a same x, y position on each of the plurality of wafers in the lot, and locating defect data signatures on the plurality of wafers in the lot based on the statistical correlation.

A method for determining electronic band structure includes partitioning, based on a location of each of a plurality of atoms forming a crystalline structure, a volume of the crystalline structure to obtain Voronoi tessellations. The method also includes constructing, based on the Voronoi tessellations, a plurality of crystal graphs and deriving, based on the plurality of crystal graphs, one or more local structural features of the crystalline structure. The method also includes feeding, into a trained machine-learning model, the one or more local structural features, one or more global structural features of the crystalline structure, and one or more species-based features of the crystalline structure. The trained machine-learning model, in response to said feeding, returns a plurality of energy values that sample a Brillouin zone of the crystalline structure.

A wafer test device includes a test interconnect to interface with a microcircuit of the wafer at a first side and an interposer to interface with the test interconnect at a second side of the test interconnect, opposite the first side. The interposer connects the test interconnect, via a printed circuit board (PCB), to a test apparatus that determines and controls test patterns that are applied to the microcircuit via the test interconnect. A support structure supports the test interconnect and the interposer. The support structure includes an inner bearing to tilt the test interconnect to match a tilt of a surface of the microcircuit. An elastomer between the test interconnect and the interposer reduces deflection of the test interconnect during a process of connecting the test interconnect to the microcircuit.

A failure pattern obtaining method and apparatus are provided. The method includes that: a chip test result picture for a wafer is obtained, the chip test result picture being marked with a plurality of failure test points; a vector for every two points among all failure test points is calculated; a plurality of failure test points having a same vector are designated as a same group; a plurality of pending failure patterns are separated from each of groups; a failure pattern is obtained based on the plurality of the pending failure patterns.

A probe card includes a sub-board, having a heating layer, connected to a probe pin. A main board is connected to the sub-board and includes a first output terminal configured to output first power received from a first power supply to the heating layer in a first mode. A power converter is configured to lower a first voltage corresponding to residual power received from the first power supply to a second voltage and output the residual power in a second mode. A second output terminal is configured to receive the residual power from the power converter and second power from a second power supply and output third power including the residual power and the second power to a device under test in the second mode. A first switch unit is connected to the first power supply, the first output terminal, and the power converter.

A method of training a neural network modeling physical phenomena of semiconductor material includes receiving plurality of training pairs corresponding to a semiconductor material. Each training pair comprises an input charge to a distinct voxel of the semiconductor material and one or more output signals generated by the distinct voxel in response to the input charge. A neural network is trained using the training pairs. The neural network models the semiconductor material and each voxel is represented in the neural network by a tensor field defined by (i) a location of the voxel within the semiconductor material and (ii) one or more physics-based phenomena within the voxel at the location.

The present invention relates to a method for open-loop or closed-loop control of the temperature of a chuck for a wafer, comprising the steps of: detecting the position of a test means for testing a wafer; determining the spatial distances between the test means and a plurality of temperature measurement means for measuring the temperature of the chuck or of a wafer supported or clamped by the chuck; selecting at least one temperature measurement means from the plurality of temperature measurement means as a reference temperature measurement means; controlling the temperature of the chuck by means of open-loop or closed-loop control on the basis of the temperature(s) of the chuck or wafer as measured by the selected one or more reference temperature measurement means.