Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

A method for detecting a physical short-circuit defect between the first metal layer and a gate below. A first detection structure and a second detection structure are arranged in parallel in a detection region or a dicing channel region on a wafer, each detection structure comprises a P-type active detection, a detection gate structure, a contact hole in the P-type active detection, gate contact holes at two ends of the detection gate structure, a metal wire connected to the contact hole in the P-type active detection, and a metal wire connected to the gate contact hole. The detection gate structure of the first detection structure and the metal wire above it at least partially overlap. However, there is no projective overlap region between the detection gate structure of the second detection structure and the metal wire—above it.

Accordingly, an improved interposer connection testing technique is provided, employing parallel pseudo-random bit sequence (PRBS) generators to test all the interconnects in parallel and simultaneously detect any correctable defects. In one embodiment, a microelectronic assembly includes an interposer electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die, the substrate having multiple conductive traces for a parallel communications bus between the IC dies. The originating IC die has a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the interposer traces. The destination IC die has a second parallel PRBS generator to create reference PRBSs with different phases, and a bitwise comparator coupled to receive the test PRBSs from the interposer traces and to compare them to the reference PRBSs to provide concurrent fault monitoring for each of the traces.

The fault detection system described provides an efficient method to test and monitor component to component connectivity in an electronic package using on chip test circuits and on chip components, which reduces the need for external testing equipment and analysis. The on chip nature allows for both real time testing in the assembly process of the electronic packages and during use of the electronic package by determining an on chip reference measurement and using the reference measurement to determine an operational status of the package.

Examples of an electronic device are described. In some examples, the electronic device includes a first shared line of a plurality of first contacts to respectively connect to a plurality of integrated circuits, a plurality of second lines of respective second contacts to respectively connect to the plurality of integrated circuits, and a third shared line of a plurality of third contacts to respectively connect to the plurality of integrated circuits. In some examples, the electronic device includes circuitry to determine whether one of the third contacts is connected to an integrated circuit based on a state of the first shared line and a state of one of the second lines that is associated with the one of the third contacts.

The present application provides a method for detecting a broken fanout wire of a display substrate, and a display substrate, and belongs to the field of display technology. In the method for detecting a broken fanout wire, the display substrate includes a base substrate having first and second surfaces opposite to each other, and a plurality of connection structures disposed at intervals on the first surface; and each connection structure includes first and second pads and a fanout wire electrically connecting the first pad to the second pad. The method for detecting a broken fanout wire includes: forming at least one detection unit, which includes: connecting at least two connection structures in series through a connecting part; and measuring a head and an end of the detection unit to obtain resistance of the detection unit, and determining whether there is a broken fanout wire in the detection unit.

Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.

A deteriorated section identifying unit refers to correspondence information that defines a deteriorated section of a plurality of bonding sections to the emitter electrode surface to which the first bonding wires are connected, for a combination of temporal change of a first voltage that is a difference between a potential at a collector main terminal and a potential at the emitter main terminal and temporal change of a second voltage that is a difference between a potential at the emitter reference terminal and a potential at the emitter main terminal, and identifies the deteriorated section corresponding to a combination of temporal change of the first voltage measured by a first voltage measuring circuit and temporal change of the second voltage measured by a second voltage measuring circuit.

Techniques and apparatuses are provided for detecting a short circuit between pins of an integrated circuit package. The tested pins can be adjacent or non-adjacent on the package. Various types of short circuits can be detected, including resistive, diode and capacitive short circuits. Additionally, short circuits of a single pin can be tested, including a short circuit to a power supply or to ground. The test circuit includes a current mirror, where the input path has a first path connected to a first pin and a parallel second path connected to a second pin. A comparator is connected to the output path of the current mirror. By controlling the on and off states of transistors in the first and second paths, and evaluating the voltage of the output path, the short circuits can be detected.

An integrated circuit chip is attached to a support that includes first conductive elements. First conductive pads are located on the integrated circuit chip and are electrically coupled to the first conductive elements by conductive wires. The integrated circuit chip further includes a conductive track. A switch circuit is provided to selectively electrically connect each first conductive pad to the conductive track. To test the conductive wires, a group of first conductive pads are connected by their respective switch circuits to the conductive track and current flow between corresponding first conductive elements is measured.