A method for the testing of optoelectronic chips which are arranged on a wafer and have electrical interfaces in the form of contact pads and optical interfaces which are arranged to be fixed relative thereto in the form of optical deflection elements, e.g., grating couplers, with a specific coupling angle. The wafer is adjusted in three adjustment steps with one of the chips relative to a contacting module such that the electrical interfaces of the chip and contacting module contact one another, and the optical interfaces of the chip and contacting module occupy a maximum position of the optical coupling.

A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT, and a plunger assembly detachably coupled with the socket structure. The plunger assembly includes a multi-layered structure having at least an interposer substrate sandwiched by a top socket and a nest.

There is provided an insertion/extraction mechanism for having one or multiple block members being inserted into or extracted from a frame member forming an intermediate connection member that is disposed between a first member having multiple first members and a second member having multiple second terminals and electrically connects the first terminals and the second terminals, the block member having multiple connection terminals for electrically connecting the first terminals and the second terminals. The insertion/extraction mechanism comprises a first engaging unit and a second engaging unit that are engaged with a first engaged portion and a second engaged portion of the block member, respectively, thereby holding the block member.

Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG. The physical contacting to the topside of the wafer is noncontaminating and noninvasive to the semiconductor layers.

A chip testing board and a chip testing method are provided. The testing board includes a first conductive layer, a second conductive layer and a third conductive layer, wherein the first conductive layer is located on a substrate for electrical connection with a first power connection point of a chip, and one side of the first conductive layer leads to a first test point; the second conductive layer is located on the first conductive layer for electrical connection with a second power connection point of the chip, and one side of the second conductive layer leads to a second test point; and the third conductive layer is located on the second conductive layer for electrical connection with a third power connection point of the chip, and one side of the third conductive layer leads to a third test point.

A semiconductor device with contact check circuitry is provided. The semiconductor device includes a plurality of pads, an internal circuit, and a contact check circuit. The plurality of pads includes a first pad and a second pad. The internal circuit is coupled to the plurality of pads. The contact check circuit, at least coupled to the first pad and the second pad, is used for checking, when the semiconductor device is under test, contact connections to the first pad and the second pad to generate a check result signal according to comparison of a first test signal and a second test signal received from the first pad and the second pad with at least one reference signal.

An embodiment optical circuit wafer includes a plurality of unit sections formed on a wafer. The plurality of unit sections are formed in each of first dies, second dies, and third dies. Further, each of the plurality of unit sections includes electrical pads formed in a common layout. Further, each of the plurality of unit sections includes optical input/output ports formed in a common layout. The input/output ports are, for example, grating couplers. Further, each of the plurality of unit sections includes optical circuits. The optical circuits have different circuit structures from one another.

A semiconductor wafer and a multi-chip parallel testing method are provided. The semiconductor wafer includes a plurality of chips, a plurality of test pads, and a test control circuit. The test pads receive a plurality of test signals from a test fixture. The test control circuit is electrically connected to the chips and the test pads, selects at least one selected test signal from the test signals, generates a plurality of broadcast test signals according to the at least one selected test signal, and provides the broadcast test signals to the chips in parallel.

The present invention relates to a test socket having a thin structure that can reduce durability degradation of a contact itself, have excellent electrical characteristics in processing high-speed signals, and can extend a service life thereof, and relates to spring contacts suitable thereto. The test socket according to the present invention includes: a plurality of spring contacts (100) each of which includes an upper contact pin (110) and a lower contact pin (120) that are assembled cross each other, and a spring (130) supporting the upper and lower contact pins (110 and 120); a main plate (1110) having a plurality of accommodating holes (1111) in which the respective spring contacts (100) are accommodated, with first openings (1113); and a film plate (1120) provided on a lower portion of the main plate (1110), and having second openings (1121).

A verification probe system is configured to verify an automated test platform and includes: an integrated circuit test probe assembly; and a moveable platform configured to position the integrated circuit test probe assembly proximate one of more conductive pins included within a test socket assembly of the automated test platform.