A testing circuit includes a first circuit and a second circuit. The first circuit has a first capacitor and a second capacitor. The first circuit is configured to transfer at least a portion of a first voltage across the first capacitor to the second capacitor. The second circuit has the first capacitor and the second capacitor. The second circuit is configured to transfer at least a portion of a second voltage across the second capacitor to the first capacitor.

The present disclosure provides a process corner detection circuit and a process corner detection method. The process corner detection circuit includes: M ring oscillators disposed inside a chip, M≥1, where types of N-type transistors in the M ring oscillators are not exactly the same, and types of P-type transistors in the M ring oscillators are not exactly the same; transistor types of the M ring oscillators include all transistor types used in the chip; the ring oscillators include symmetric ring oscillators and asymmetric ring oscillators; types of N-type transistors and P-type transistors in the symmetric ring oscillators are the same; and types of N-type transistors and P-type transistors in the symmetric ring oscillators are different.

Embodiments disclosed herein generally relate to a method, system, and non-transitory computer readable medium for classifying an outlier in time series data collected by a sensor positioned in a substrate processing chamber. The client device receives time series data from the sensor positioned in the substrate processing chamber. The client device converts the time series data to a bounded uniform signal. The client device identifies signal sub-segments that do not match an expected behavior. The client device classifies the identified sub-segments that do not match the expected behavior.

The method may be used for measuring an electric property of a magnetic tunnel junction used in an embedded MRAM memory for example. The method uses a multi point probe with a plurality of probe tips for contacting a designated area of the test sample, which is electrically insulated from the part of the test sample which is to be tested. Electrically connections are placed underneath the magnetic tunnel junction and goes to the designated area.

A maintenance tool for semiconductor process equipment and components. Sensor data is evaluated by machine learning tools to determine when to schedule maintenance action.

A chip crack detection apparatus is provided, to reduce interference to a function circuit while implementing die crack detection. The apparatus includes a function circuit (110) and a die crack detection module (120) located surrounding the function circuit (110). The die crack detection module (120) includes a front-end-of-line device layer (121) and a laminated structure (122) disposed on the front-end-of-line device layer (121), a conducting wire (L) is formed in the laminated structure (122), and one or more first capacitors (C1) are formed at the front-end-of-line device layer (121). A first end of the conducting wire (L) is configured to connect to a positive electrode of a power supply, and a second end of the conducting wire (L) is configured to connect to a negative electrode of the power supply.

A method includes tracing from an observation point in a circuit to an input of the circuit to produce a cone of influence that includes a plurality of components of the circuit. The plurality of components is connected at a plurality of nodes in the cone of influence and the plurality of components includes a plurality of logic elements. The method also includes, for each node of the plurality of nodes, determining an observability probability that a logical high or low value at a corresponding node propagates to the observation point. The method further includes determining a weighted soft error probability for each logic element of the plurality of logic elements and determining a weighed soft error failure mode distribution for the cone of influence.

A tester apparatus is described. Various components contribute to the functionality of the tester apparatus, including an insertion and removal apparatus, thermal posts, independent gimbaling, the inclusion of a photo detector, a combination of thermal control methods, a detect circuitry in a socket lid, through posts with stand-offs, and a voltage retargeting.

A testing circuit includes a first circuit and a second circuit. The first circuit has a first capacitor and a second capacitor. The first circuit is configured to transfer at least a portion of a first voltage across the first capacitor to the second capacitor. The second circuit has the first capacitor and the second capacitor. The second circuit is configured to transfer at least a portion of a second voltage across the second capacitor to the first capacitor.

A method includes receiving system test data for a plurality of electronic systems. Each of the electronic systems includes a plurality of electronic components. The method also includes determining a relationship between a set of electronic components and the electronic systems upon which the electronic components of the set of electronic components are assembled and receiving manufacturing attributes including spatial data for the set of electronic components. The method further includes selecting a data subset from the system test data corresponding to a subgroup of the set of electronic components. The subgroup includes components within an area defined on a substrate according to a spatial pattern and that is fewer than all of the set of electronic components on the substrate. Additionally, the method includes identifying an outlier relative to the data subset and communicating information about the outlier to at least one of a system or a component manufacturer.