An integrated circuit may include a first semiconductor device including a first through-silicon via configured for electrically coupling a first bump pad to a second bump pad, and may be configured to buffer a first internal test signal generated by a test signal inputted through the first bump pad and generate a first detection signal. The integrated circuit may include a second semiconductor device including a second through-silicon via configured for electrically coupling a third bump pad to a fourth bump pad, and may be configured to buffer a second internal test signal generated by the test signal inputted through the third bump pad and generate a second detection signal. The third bump pad may be electrically coupled with the second bump pad.

A device comprises a first die; and a second die stacked below the first die with interconnections between the first die and the second die. A least one of the first die or the second die has a circuit for performing a function and provides a functional path. Each of the first and second dies comprise a plurality of latches, including a respective latch corresponding to each one of the interconnections; and a plurality of multiplexers. Each multiplexer is connected to a respective one of the plurality of latches and arranged for receiving and selecting one of a scan test pattern or a signal from the functional path for outputting during a scan chain test of the first die and second die.

Embodiments of the present disclosure relate to solutions for introducing personalization data in nonvolatile memories of a plurality of integrated circuits, comprising writing in the nonvolatile memory of a given integrated circuit a static data image, corresponding to an invariant part of nonvolatile memory common to the plurality of integrated circuits, and a personalization data image representing data specific to the given integrated circuit.

A testing system for electrical interconnects having a removable device under test printed circuit board (DUT PCB) that electrically connects with the electrical testing components of the system. A removable top plate is placed on top of the DUT PCB and is locked in place by a plurality of locking posts that selectively connect to cam surfaces in the top plate that pull the top plate down sandwiching the DUT PCB between the top plate and the electrical testing components of the system. An actuator is also presented that presses the device under test into the electrical interconnect at increments where tests are performed on one, some or all of the contact points of the electrical interconnect. This information is then analyzed and graphed to assist with determine the optimum force and/or height to use during actual use.

A semiconductor integrated circuit device (1000) includes: a first semiconductor chip CHP1 having a first circuit; and a second semiconductor chip (CHP2) having a second circuit and differing from the first semiconductor chip (CHP1). The semiconductor integrated circuit device (1000) further includes a control circuit (BTCNT) for controlling an operation of the first circuit and an operation of the second circuit in accordance with a control signal in a burn-in test, and the control circuit (BTCNT) controls the first circuit and the second circuit such that an amount of stress applied to the first semiconductor chip (CHP1) due to an operation of the first circuit and an amount of stress applied to the second semiconductor chip (CHP2) due to an operation of the second circuit differ from each other in the burn-in test.

A semiconductor package test apparatus is provided. A semiconductor package test apparatus comprises a test board including a plurality of sensors, a chamber into which the test board is loaded, and a controller configured to control a temperature of the chamber, wherein the controller adjusts the temperature using the plurality of sensors.

A semiconductor module including a semiconductor element which is bonded to a wiring pattern part and connects or disconnects two main electrode terminals to or from each other according to a drive signal applied to a gate electrode terminal, includes a deterioration detecting circuit configured to use one main electrode terminal of the two main electrode terminals of the semiconductor element with an applied DC voltage, as a reference potential, and detect deterioration of a joining part of the semiconductor element on the basis of a gate voltage which is the voltage between the one main electrode terminal and the gate electrode terminal and an inter-main-electrode voltage which is the voltage between the one main electrode terminal and the other main electrode terminal, and outputs an alarm signal.

The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.

The disclosure relates to an integrated circuit and associated method and packaged integrated circuit. The integrated circuit comprises a first pad; a second pad; an active element having a node that is capacitively coupled to the first and second pads; a voltage or current source connected to the first pad; and a detection module connected to the second pad and configured to determine an electrical continuity between the second pad and the first pad.

A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.