Techniques are disclosed related to determining a modulation quality measurement of a device-under-test (DUT). A modulated signal is received from a source a plurality of times, and each received modulated signal is transmitted to each of a first vector signal analyzer (VSA) and a second VSA. The first VSA and the second VSA demodulate the received modulated signals to produce first error vectors and second error vectors, respectively. A cross-correlation calculation is performed on the first error vectors and second error vectors of respective received modulated signals to produce a cross-correlation measurement, and the cross-correlation measurement is averaged over the plurality of received modulated signals. A modulation quality measurement is determined based on the averaged cross-correlation measurement.

A method is provided for testing discrete output signals of a device-under-test (DUT). The method includes receiving an electrical quantity at each conductive path of a plurality of conductive paths that are each coupled to respective discrete output signals of the DUT in one-to-one correspondence. The method further includes controlling application of the electrical quantity to each of the conductive path independent of application of the electrical quantity along the other conductive paths, so that a the electrical quantity is applied simultaneously to all of the conductive paths, the electrical quantity applied to each conductive path being toggled at a unique frequency having a unique period. Accordingly, a characteristic of the electrical quantity at each of the respective test output conductors over the duration of the longest period of the unique periods is indicative of any disturbance between the discrete output signals associated with the test output conductor and all of the other discrete output signals.

A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

A method of detecting crosstalk for a digital isolator having first and second channels including two die with channels including a transmit side, receive side, with 1 die including a capacitive barrier for each channel. A first clock signal at a first frequency in a first pulse pattern and a second clock signal at a second frequency in a second pulse pattern are configured, wherein the pulse patterns have a phase difference. The transmit side of the channels each encode their received clock pulse pattern, then modulate with a carrier frequency to provide a fc1 and a fc2 signal, respectively. The receive side of the channels demodulate received signals during a rising or falling edge of their clock signal to generate a delayed received version of the first and second clock pulse pattern. Missing pulses are identified by comparing the delayed received clock pulse patterns to their clock pulse patterns.

A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

A duty cycle measurement circuit obtains differential duty cycle measurements corresponding to the duty cycle of a signal at two or more different locations along a propagation path. The differential duty cycle measurements may include measurements of an input duty cycle and measurements of an output duty cycle. The duty cycle measurements may be acquired by use of duty-cycle-to-voltage converter circuitry. The duty cycle measurements may be used to determine a measure of the duty cycle deterioration of the propagation path, and an adjustment factor to compensate for the measured duty cycle deterioration.

A method for identifying the noise figure of a device under test is described. A signal generator that outputs the modulated signal, a device under test and an analyzer are provided. The signal generator is connected with the analyzer directly wherein at least two error vector magnitude measurements are performed. The signal generator is connected with the device under test and the device under test is connected with the analyzer wherein at least two error vector magnitude measurements are performed. The noise contribution of the device under test is determined from the error vector magnitude measurements performed. A gain measurement is performed on the device under test. The noise figure of the device under test is calculated based on the noise contribution of the device under test obtained and the gain of the device under test obtained. Further, a measurement system is described.

A glitch measurement device is coupled to a circuit under-test and includes a counter circuitry and a detector circuitry. The counter circuitry is coupled to the circuit under-test, and is configured to perform a first counting operation according to an input signal transmitted to the circuit under-test to generate a first count signal, and to perform a second counting operation according to an output signal outputted from the circuit under-test to generate a second count signal. The detector circuitry is coupled to the circuit under-test and the counter circuitry, and is configured to receive the first count signal and the second count signal according to the input signal, and to generate a glitch indication signal according to the first count signal and the second count signal.

An interference detection device and a detection sensitivity adjusting method are provided. A signal generating circuit generates a detection signal. A delay circuit delays the detection signal to generate a plurality of delay signals with different delay time. A decision circuit selects one of the delay signals according to a first section signal for comparing with the detection signal to generate an interference detection result, where the delay signals are used for adjusting the detection sensitivity of the interference detection device.

An eye diagram measurement device includes a first mapping circuitry, a count circuitry, a second mapping circuitry and a memory circuitry. The first mapping circuitry maps one of plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counter circuitry performs a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits, to generate a plurality of count signals. The second mapping circuitry maps the count signals respectively to a plurality of eye diagram measurement signals corresponding to a present phase. The memory circuitry stores the eye diagram measurement signals in order to provide the eye diagram measurement signals to an external system for generating an eye diagram measurement result of the electronic device.