A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin.

A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.

A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.

A method for an improved characterization of standard cells in a circuit design process is disclosed. Adaptive body biasing is considered during the design process by using simulation results of a cell set, a data-set for performance of the cell set, and a data-set for a hardware performance for a slow, typical and fast circuit property. Static deviations in a supply voltage are considered by determining a reference performance of a cell and a reference hardware performance monitor value at a PVT corner. A virtual regulation and adapting of body bias voltages of the cell set is performed such that the reference performance of the cell or the reference hardware performance monitor value will be reached at each PVT corner and for compensating the static deviation in the supply voltage. The results are provided in a library file.

An inspection system configured to inspect a device within a substrate is provided. The inspection system includes an inspection module, an alignment module, a supporting device and a fixing device. The inspection module has multiple testers and multiple inspection chambers. The multiple testers are allowed to be accommodated in the multiple inspection chambers, respectively. The alignment module has an aligner. The aligner is placed in an alignment space. The aligner is configured to adjust a position of the substrate to be inspected with respect to one tester of the multiple testers, which is accommodated in the alignment space. The supporting device is configured to support the tester accommodated in the alignment space from below. The fixing device is configured to fix the tester accommodated in the alignment space in cooperation with the supporting device.

A method and apparatus for determining jitter, a storage medium and an electronic device are disclosed. The method for determining jitter includes: determining a plurality of measurement time points for an output signal from an integrated circuit (IC); identifying one or more jitter points from the plurality of measurement time points by comparing the output signal with a predetermined signal at the plurality of measurement time points; and determining a jitter of the output signal of the IC based on the one or more jitter points. The jitter of the output signal of an IC chip can be determined without relying on any other additional equipment.

Techniques to perform semiconductor testing are described. Test equipment may test a chiplet for compliance with a semiconductor specification. A test device may connect to a test package with a model chiplet and a device under test (DUT) chiplet. The model chiplet may comprise a known good model (KGM) of the semiconductor specification. The test device may use the model chiplet to test the DUT chiplet. Other embodiments are described and claimed.

The present invention relates to a system and method for calculating measurement uncertainty and determining measurement decision risk. Measurement uncertainty is calculated based on a plurality of error contributors. Measurement decision risk is evaluated using the measurement uncertainty, and mitigation strategies are applied to lower the probability of false acceptance and the probability of false rejection.

A computer implemented method may include executing a first simulation test for testing a device under test (DUT) and a corresponding test environment; saving a snapshot image of the DUT and of the corresponding test environment upon completion of initialization actions included in the first simulation test to configure the DUT; compiling a DUT part of a second simulation test into the saved snapshot image of the DUT to obtain a restore image for the DUT; loading the restore image of the DUT and restoring the snapshot image of the test environment; loading a test environment part of the second simulation test; and executing the second simulation test on the DUT and corresponding test environment.

A computerized method for IC classification, outlier detection and/or anomaly detection comprising using at least one hardware processor for testing each of the plurality of ICs in accordance with an IC design on a wafer, wherein the IC design comprises a plurality of sensors. The at least one hardware processor is used for testing each of the plurality of ICs by: collecting a plurality of sensor values, the plurality of sensor values including sensor values from each of the plurality of sensors; comparing the plurality of sensor values to a classification scheme, thereby obtaining a classification for each tested IC; and recording the classification of the tested IC.

A method and an apparatus for reducing an effect of local process variations of a digital circuit on a hardware performance monitor includes measuring a set of performance values (c.sub.1, c.sub.2 . . . c.sub.n) of the digital circuit by n identical hardware performance monitors, where n is a natural number greater than 1, determining an average value c.sub.mean of the measured performance values (c.sub.1, c.sub.2 . . . c.sub.n), as an approximation of an ideal performance value c.sub.0, selecting one performance value c.sub.j of the set of performance values (c.sub.1, c.sub.2 . . . c.sub.n) by a controller, comparing the performance value c.sub.j with a reference value c.sub.ref by a controller the controller, resulting in a deviation value Δc, and controlling an actuator by using the deviation Δc for regulating the local global process variations to the approximation c.sub.mean of the ideal performance value c.sub.0.