A method and an apparatus for reducing the effect of local process variations of a digital circuit on a hardware performance monitor includes measuring a set of performance values c.sub.n of the digital circuit by n identical hardware performance monitors, where n is a natural number greater than 1, determining an average value c.sub.mean of the measured performance values c.sub.n, as an approximation of an ideal performance value c.sub.0, selecting one performance value c.sub.j of the set of performance values c.sub.n by a signal converter, comparing the performance value c.sub.j with a reference value c.sub.ref by a controller, resulting in a deviation value c, and controlling an actuator by using the deviation c for regulating the local global process variations to the approximation c.sub.mean of the ideal performance value c.sub.0.

A system includes at least one tool, a storage device and a processor. The at least one tool performs semiconductor fabrication processes on at least one wafer, in which the at least one tool includes sensors. The storage device stores computer program codes. The processor executes the computer program codes in the storage device for: modeling profiles from the sensors to generate a modeling result; extracting features from the modeling result corresponding to the modeled profiles; based on the extracted features, extracting scores each representing a degree of the at least one wafer being processed by the at least one tool; and based on the extracted scores, displaying a ranking for fault detection of the at least one wafer.

An additional test pattern acquiring unit acquires a test pattern, which is not yet executed to the semiconductor device serving as a target of executing an additional test among test patterns stored in a test pattern information DB, as an additional test pattern with reference to a semiconductor manufacturing history information DB. Also, an additional test transmitting unit transmits the additional test pattern acquired by the additional test pattern acquiring unit to the semiconductor device serving as the target of the additional test through a network. An additional test result acquiring unit acquires a test execution result together with an ID of the semiconductor device, and a registration unit registers identification information of the executed test pattern, an execution result of the test pattern, and an execution timing of the test in a semiconductor product history information DB so as to be associated with the acquired ID of the semiconductor device.

A test and measurement system for parallel waveform analysis acquires waveforms resulting from performing tests on a device under test (DUT) and performs, at least partially in parallel, respective analyses of the waveforms resulting from performing tests on the DUT. The system also acquires a first waveform resulting from performing a first test with an oscilloscope on a DUT and performs analysis of the first waveform at least partially in parallel with acquiring a second waveform. Additionally, the system tracks a plurality of testing assets using inventory information of a plurality of testing equipment on the network and enables remote users to access equipment logs and results of the respective analyses of the waveforms stored on a cloud computing system for performance of analytics.

A method for testing system-on-a-chip (SoC) for faults at subthreshold or substantially at threshold operating voltages includes the steps of testing the SoC for fault at a favorable operating voltage, the testing including measuring a metric characterizing the fault at the favorable operating voltage to obtain a first metric value; and retesting the SoC for the fault at a first operating voltage upon the first metric value at the favorable operating voltage being correlated, according to a metric correlation establishing a correlation relationship between the favorable operating voltage and the first operating voltage, to a second metric value at the first operating voltage within a predictive interval of the metric correlation.

A batch testing system includes a test device, a plurality of machines to be tested and a server. The test device writes a BIOS with a RMT test to each machine to be tested, and starts each machine to be tested to run the RMT test, and then each machine to be tested writes a test result to a specific storage location in a baseboard management controller thereof. When entering an operating system, each machine to be tested reads and analyzes the test result at the specific storage location to output an analysis result, and then transmits the analysis result to the server through a network. The server receives and counts the analysis results transmitted by the machines to be tested. Therefore, the batch testing system can deploy the RMT test, and no intervention from operators is required in the whole process, which is suitable for the production testing stage.

A method and associated system. The method includes steps of: (a) a voltage bin is selected from of a set of voltage bins, each voltage bin having a different range of frequencies based on the highest operating frequency and the lowest operating frequency specified for an integrated circuit chip not previously tested; (b) a functional path test is performed on a selected path of a set of testable data paths of the integrated circuit chip not previously tested; (c) if the integrated circuit chip fails the functional path test, then a current supply voltage value is changed to a voltage value associated with a not previously selected voltage bin; (d) a not previously tested path of the set of testable paths is selected. Steps (b), (c) and (d) are repeated until every path of the set of testable paths has been tested.

A method of testing a tester, comprising testing electronic units using a plurality of sites in order to obtain first bin assignment, instructing the tester to perform a tester quality test if conditions C.sub.iQA,1 and C.sub.iQA,2 are met, the tester quality test comprising performing a second plurality of tests on an electronic unit using a first site, thereby obtaining second bin assignment for the electronic unit, the second bin assignment being representative of passing or failing of the electronic unit of the second plurality of tests with respect to at least one second test criteria, wherein C.sub.iQA,1 is met if passing first bin assignment has been obtained for said electronic unit connected to the tester using the first site, and wherein C.sub.iQA,2 is met if data representative of passing first bin assignment obtained for electronic units which have been tested on the first site, meets a quality criteria.

Disclosed is a test and measurement instrument including a plurality of ports. The ports are configured to source a test signal into a device under test (DUT), and receive a signal response from the DUT. The test and measurement instrument also includes a measurement unit configured to measure the signal response. The test and measurement instrument further includes a processor configured to compare the signal response to a data structure. The processor also determines a classification of, and/or connections to, at least one DUT component coupled to at least one of the ports based on results of the comparison.

An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.