A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.

A package comprises a photonic integrated circuit (PIC) with a modulator having a first modulator input, and a PIC interconnect region within two millimeters or fifty microns from the modulator. Additionally, an electric integrated circuit (EIC) is included with a driver circuit and an EIC interconnect region within two millimeters or fifty microns from the driver circuit. The driver circuit is electrically connected to the first modulator input via the EIC interconnect region, a first metal interconnect, and the PIC interconnect region. The modulator receives a temperature-dependent bias voltage, where the temperature dependence of the bias voltage inversely matches the temperature dependence of the modulator across an extended temperature range.