Digital systems formed on integrated circuits may include sequential logic circuitry. The sequential logic circuitry may form at least part of a finite state machine that records different logical states. The sequential logic circuitry may include a first latching circuit and a second latching circuit that each latch bits onto their respective outputs when clocked at different levels. The first latching circuit may output a first bit. Combinational logic circuitry may be distributed on both sides of the first latching circuit such that a combinational logic circuit interposed between the first and second latching circuits generates a second bit based on at least the first bit. The first and second bits may record one of two possible finite logical states of the sequential logic circuitry. By distributing combinational logic circuitry on two sides of a given latching circuit, dynamic power consumption by the sequential logic circuitry may be optimized.

A method includes calculating a first position encoded pattern based on a first data pattern, and using an automata processor to compare the first position encoded pattern to a second position encoded pattern to identify a second data pattern within the first data pattern.

A method includes calculating a first position encoded pattern based on a first data pattern, and using an automata processor to compare the first position encoded pattern to a second position encoded pattern to identify a second data pattern within the first data pattern.

The embodiments of the present disclosure provide an equipment control processing method and device. The method includes: determining an action type according to an action of the component to be controlled; determining a target action logic code class according to the action type and a plurality of pre-created action logic code classes, wherein the action logic code class is created according to the action types extracted from the actions of a plurality of the components to be controlled; creating an action object corresponding to the component to be controlled according to the target action logic code class; correlating control signal corresponding to the action of the component to be controlled and the action object corresponding to the component to be controlled, and storing correlation between the control signal and the action object, so as to implement control processing on the component to be controlled according to the correlation between the control signal and the action object. The device is used to perform the method above. The method and device provided by the embodiments of the present disclosure improve the equipment control efficiency.

The embodiments of the present disclosure provide an equipment control processing method and device. The method includes: determining an action type according to an action of the component to be controlled; determining a target action logic code class according to the action type and a plurality of pre-created action logic code classes, wherein the action logic code class is created according to the action types extracted from the actions of a plurality of the components to be controlled; creating an action object corresponding to the component to be controlled according to the target action logic code class; correlating control signal corresponding to the action of the component to be controlled and the action object corresponding to the component to be controlled, and storing correlation between the control signal and the action object, so as to implement control processing on the component to be controlled according to the correlation between the control signal and the action object. The device is used to perform the method above. The method and device provided by the embodiments of the present disclosure improve the equipment control efficiency.

An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

There is expected a technique for restricting a server function without affecting a driving machine in the case where memory usage is increased. A controller includes a memory, a program execution section controlling a driving machine in accordance with a control program, and an OPC-UA server communicating with an external machine. The OPC-UA server includes: a function execution section, executing a function utilizing a memory region on the memory in response to a request from the external machine; a monitoring section monitoring usage of the memory; and a restriction section, stopping the above function of the OPC-UA server based on the fact that the usage has exceeded a predetermined threshold.

There is expected a technique for restricting a server function without affecting a driving machine in the case where memory usage is increased. A controller includes a memory, a program execution section controlling a driving machine in accordance with a control program, and an OPC-UA server communicating with an external machine. The OPC-UA server includes: a function execution section, executing a function utilizing a memory region on the memory in response to a request from the external machine; a monitoring section monitoring usage of the memory; and a restriction section, stopping the above function of the OPC-UA server based on the fact that the usage has exceeded a predetermined threshold.

Machine logic (for example, software) for managing the nuisance level characteristic (for example, nuisance-level sound) of another user's electronic, media-connected device. The machine logic considers contextual information (such as where the user is presently located and whether it is appropriate for the user's device to be emanating a loud, nuisance level volume).