The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.

The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.

Systems and methods related to a cryogenic-CMOS interface for controlling qubit gates are provided. A system for controlling qubit gates includes a first device comprising a quantum device including qubit gates. The system further includes a second device comprising a control system configured to operate at the cryogenic temperature. The control system includes charge locking circuits, where each of the charge locking circuits is coupled to at least one qubit gate via an interconnect such that each of the charge locking circuits is configured to provide a voltage signal to at least one qubit gate. The control system further includes a control circuit comprising a finite state machine configured to provide at least one control signal to selectively enable at least one of the charge locking circuits and to selectively enable a provision of a voltage signal to a selected one of the charge locking circuit.

A test and measurement instrument including a digital-to-analog converter having an output sample rate configured to receive a digital sample waveform and a reference clock and output an analog waveform at the sample rate, a waveform synthesizer configured to receive an input waveform having a baud rate and output a digital sample waveform having a baud rate less than the sample rate of the digital-to-analog converter, and a port configured to output the analog waveform.

Computationally efficient mixed precision floating point waveform generation takes advantage of the high-speed generation of waveforms with single-precision floating point numbers while reducing the generally unacceptable loss of precision of pure single-precision floating point to generate any waveform that repeats in 2π. This approaches computes a reference phase in double precision as the modulus of the phase with 2π and then computes offsets to that value in single precision. The double precision reference phase is recomputed as needed depending on how quickly the phase grows and how large a machine epsilon is desired.

Apparatus and method for specifying quantum operations such as qubit rotations in a quantum instruction. For example, one embodiment of an apparatus comprises: a quantum instruction processing pipeline to process a quantum instruction having one or more opcodes to specify quantum operations and one or more operands and/or fields to specify values to be used to perform the quantum operations; a quantum waveform synthesizer to synthesize a waveform to control a qubit based on the values specified by the operands and/or fields of the quantum instruction.

Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

A waveform synthesizer comprises a controllable oscillator for generating an oscillator waveform having an oscillator cycle; a reference input for accepting a reference signal having a reference cycle; and a waveform detector coupled to said oscillator and said reference input. The waveform detector is arranged to sample said waveform in response to said reference input and to determine waveform information about said oscillator. The waveform information is operative to adjust said controllable oscillator.

An arbitrary waveform sequencer device for playing a list of at least a first and a second arbitrary waveform file in a sequence is provided. The arbitrary waveform sequencer device comprises a list increment condition control unit configured to control an increment from the first to the second arbitrary waveform file as a function of an increment condition, and a transition control unit configured to control a timing of the increment.

The disclosure describes various aspects of a system with scalable and programmable coherent waveform generators. A network and digital-to-analog conversion (DAC) cards used by the network are described where each DAC card has a clock divider/replicator device with an input SYNC pin, a digital logic component, and one or more DAC components, and each output of the DAC components is used to control optical beams for a separate qubit of a quantum information processing (QIP) system. The network also includes a first distribution network to provide a clock signal to the clock divider/replicator device in the DAC cards, and a second distribution network to provide a start signal to the DAC cards, where the start signal is used by the digital logic component in the DAC card to assert the input SYNC pin when the start signal is asserted unless it is masked by the digital logic component.